Semiconductor device having dummy active fin patterns

Patent metadata

Field	Value
Publication number	US-9929156-B2
Application number	US-201615372840-A
Country	US
Kind code	B2
Filing date	Dec 8, 2016
Priority date	Apr 5, 2016
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a circuit region and a dummy region, the dummy region including a first dummy region and a second dummy region, and the circuit region including a first circuit region opposing the first dummy region and a second circuit region spaced apart from the first dummy region,
circuit active fin patterns in the circuit region;
dummy active fin patterns in the dummy region at a same pitch as a pitch of the circuit active fin patterns;
circuit gate lines in the circuit region; and
dummy gate lines in the dummy region at a same pitch as a pitch of the circuit gate lines,
wherein a density of the dummy active fin patterns in the first dummy region is different from a density of the circuit active fin patterns in the first circuit region, and
wherein a density of the dummy active fin patterns in the second dummy region is different from a density of the dummy active fin patterns in the first dummy region.

2. The semiconductor device as claimed in claim 1 , wherein one of the density of the circuit active fin patterns in the first circuit region and the density of the dummy active fin patterns in the first dummy region is higher than an average density of the circuit active fin patterns in the first and second circuit regions, and the other is lower than the average density of the circuit active fin patterns in the first and second circuit regions.

3. The semiconductor device as claimed in claim 2 , wherein:
the density of the circuit active fin patterns in the first circuit region is higher than the average density of the circuit active fin patterns in the first and second circuit regions, and
the density of the dummy active fin patterns in the first dummy region is lower than the average density of the circuit active fin patterns in the first and second circuit regions.

4. The semiconductor device as claimed in claim 2 , wherein:
the density of the circuit active fin patterns in the first circuit region is lower than the average density of the circuit active fin patterns in the first and second circuit regions, and
the density of the dummy active fin patterns in the first dummy region is higher than the average density of the circuit active fin patterns in the first and second circuit regions.

5. The semiconductor device as claimed in claim 1 , wherein the dummy active fin patterns in the second dummy region are at a density corresponding to an average density of the circuit active fin patterns in the first and second circuit regions.

6. The semiconductor device as claimed in claim 1 , wherein:
the first circuit region includes a plurality of circuit portions,
the plurality of circuit portions of the first circuit region includes a high-density circuit region and a low-density circuit region,
the first dummy region includes a plurality of dummy portions corresponding to the plurality of circuit portions of the first circuit region, and
the plurality of dummy portions of the first dummy region includes a low-density dummy region opposing the high-density circuit region and a high-density dummy region opposing the low-density circuit region.

7. The semiconductor device as claimed in claim 6 , wherein:
the high-density circuit region is a region in which a density of disposition of the circuit active fin patterns is higher than the low-density circuit region, and
the high-density dummy region is a region in which a density of disposition of the dummy active fin patterns is higher than the low-density dummy region.

8. The semiconductor device as claimed in claim 6 , wherein the number of the circuit active fin patterns in the high-density circuit region is higher than the number of the circuit active fin patterns in the low-density circuit region.

9. The semiconductor device as claimed in claim 1 , wherein:
the circuit active fin patterns and the dummy active fin patterns are arranged on virtual linear lines extended in a first direction, and
the circuit gate lines and the dummy gate lines are arranged on virtual linear lines extended in a second direction perpendicular to the first direction.

10. The semiconductor device as claimed in claim 1 , wherein, in the dummy region, a density of the dummy gate lines is higher than a density of the dummy active fin patterns.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Oh In Wook
• Yang Jae Seok
• Lee Jong Hyun
• Lee Hyun Jae
• Hwang Sung Wook

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H01L27/0886 Primary

  Electricity · mapped topic

• G06F17/5072

  Physics · mapped topic