Method of forming Fin-FET

Patent metadata

Field	Value
Publication number	US-9385048-B2
Application number	US-201314018439-A
Country	US
Kind code	B2
Filing date	Sep 5, 2013
Priority date	Sep 5, 2013
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

The present invention provides a method of forming Fin-FET. A substrate with an active region and a dummy region are defined thereon. A plurality of first fins and second fins are formed in the active region, and a plurality of dummy fins are formed in the dummy region and the active region. A first active region is provided in the active region. A revised first active region is formed by extending the first active region to cover at least one adjacent dummy fin. Next, a first dummy region is provided in the dummy region. A first mask layout is formed by combining the revised first active region and the first dummy region. A first patterned mask layer is formed by using the first mask layout. A first epitaxial process is performed for the first fins and the dummy fins exposed by the first patterned mask layer.

First claim

What is claimed is:

1. A method of forming a Fin-FET, comprising:
providing a substrate with an active region and a dummy region defined thereon;
forming a plurality of first fins in the active region, a plurality of second fins in the active region, and a plurality of dummy fins in the dummy region and in the active region;
forming a first patterned mask layer by:
providing a first active region corresponding to the first fins in the active region;
forming a revised first active region by extending the first active region to cover at least one adjacent dummy fin in the active region;
providing a first dummy region in the dummy region; and
forming a first mask layout by combining the revised first active region and the first dummy region, wherein after forming the first mask layout, the density of the first mask layout is calculated to meet a predetermined value; and
using the first mask layout to form the first patterned mask layer; and

performing a first epitaxial process for the first fins and the dummy fins exposed by the first patterned mask layer, wherein the first patterned mask layer covers the second fins during the first epitaxial process,
forming a second patterned mask layer by:
providing a second active region corresponding to the second fins in the active region;
forming a revised second active region by extending the second active region to cover at least one adjacent dummy fin in the active region, wherein the dummy fin in the revised second active region is electrically separated from the dummy fin in the revised first active region;
providing a second dummy region in the dummy region; and
forming a second mask layout by combining the revised second active region and the second dummy region; and
using the second mask layout to form the second patterned mask layer; and

performing a second epitaxial process for the second fins and the dummy fins exposed by the second patterned mask layer.

2. The method of forming a Fin-FET according to claim 1 , wherein during the step of forming the revised first active region, the number of the dummy fin covered by the revised first active region is larger than or equal to 2.

3. The method of forming a Fin-FET according to claim 1 , wherein the first dummy region in the dummy region is adjusted if the density of the first mask layout does not meet the predetermined value.

4. The method of forming a Fin-FET according to claim 3 , wherein the first dummy region is adjusted by changing the size of each first dummy region, or by changing the number of first dummy regions.

5. The method of forming a Fin-FET according to claim 1 , wherein during the step of forming the revised second active region, the number of the dummy fin covered by the revised second active region is larger than or equal to 2.

6. The method of forming a Fin-FET according to claim 1 , wherein after forming the second mask layout, the density of the second mask layout is calculated to meet a predetermined value.

7. The method of forming a Fin-FET according to claim 6 , wherein the second dummy regions in the dummy region are adjusted if the density of the second mask layout does not meet the predetermined value.

8. The method of forming a Fin-FET according to claim 7 , wherein the second dummy region is adjusted by changing the size of each second dummy region, or by changing the number of second dummy regions.

9. The method of forming a Fin-FET according to claim 1 , wherein the second mask layout does not overlap the first mask layout.

10. The method of forming a Fin-FET according to claim 1 , further comprising forming a first gate structure crossing the first fin and the dummy fin in the active region.

11. The method of forming a Fin-FET according to claim 1 , further comprising forming a second gate structure crossing the second fin and the dummy fin in the active region.

12. The method of forming a Fin-FET according to claim 1 , further comprising forming a dummy gate structure crossing the dummy fin in the dummy region.

Assignees

• United Microelectronics Corp

Inventors

• Hong Shih-Fang
• Chiu Chung-Yi

Classifications

• H10D86/011

  comprising FinFETs · CPC title

• H10D30/0243

  using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability · CPC title

• H10D84/0193 Primary

  the components including FinFETs · CPC title

• H10D84/038 Primary

  using silicon technology, e.g. SiGe · CPC title

• H01L29/6681

  Electricity · mapped topic