Cell and macro placement on fin grid

Patent metadata

Field	Value
Publication number	US-9047433-B2
Application number	US-201313874027-A
Country	US
Kind code	B2
Filing date	Apr 30, 2013
Priority date	Feb 27, 2013
Publication date	Jun 2, 2015
Grant date	Jun 2, 2015

Abstract

A die includes at least one standard cell, which includes a first boundary and a second boundary opposite to the first boundary. The first boundary and the second boundary are parallel to a first direction. The at least one standard cell further includes a first plurality of FinFETs including first semiconductor fins parallel to the first direction. The die further includes at least one memory macro, which has a third boundary and a fourth boundary opposite to the third boundary. The third boundary and the fourth boundary are parallel to the first direction. The at least one memory macro includes a second plurality of FinFETs including second semiconductor fins parallel to the first direction. All semiconductor fins in the at least one standard cell and the at least one memory macro have pitches equal to integer times of a minimum pitch of the first and the second semiconductor fins.

First claim

What is claimed is:

1. A die comprising:
at least one standard cell comprising:
a first boundary and a second boundary opposite to the first boundary, wherein the first boundary and the second boundary are parallel to a first direction;
a first plurality of Fin Field-Effect Transistors (FinFETs) comprising first semiconductor fins parallel to the first direction, with the first semiconductor fins having a first pitch; and

at least one memory macro, wherein the at least one standard cell and the at least one memory macro are different types of cells, comprising:
a third boundary and a fourth boundary opposite to the third boundary, wherein the third boundary and the fourth boundary are parallel to the first direction; and
a second plurality of FinFETs comprising second semiconductor fins parallel to the first direction, with the second semiconductor fins have a second pitch, wherein all semiconductor fins in the at least one standard cell and all semiconductor fins in the at least one memory macro have pitches equal to integer times of a minimum pitch of the first semiconductor fins and the second semiconductor fins, and wherein one of the first pitch and the second pitch is greater than the minimum pitch, and a first distance between the first boundary and the second boundary and a second distance between the third boundary and the fourth boundary are equal to integer times of a minimum pitch, with the integer times being greater than one time.

2. The die of claim 1 further comprising:
at least one analog macro comprising:
a fifth boundary and a sixth boundary opposite to the third boundary, wherein the fifth boundary and the sixth boundary are parallel to the first direction; and
a third plurality of FinFETs comprising third semiconductor fins parallel to the first direction, wherein pitches of all semiconductor fins in the at least one analog macro are equal to integer times of the minimum pitch.

3. The die of claim 1 further comprising:
at least one Input/output (JO) macro comprising:
a fifth boundary and a sixth boundary opposite to the third boundary, wherein the fifth boundary and the sixth boundary are parallel to the first direction; and
a third plurality of FinFETs comprising third semiconductor fins parallel to the first direction, wherein pitches of all semiconductor fins in the at least one IO macro are equal to integer times of the minimum pitch.

4. The die of claim 1 , wherein substantially all semiconductor fins of all FinFETs in the die have lengthwise directions parallel to the first direction, and wherein substantially all pitches of all semiconductor fins of all FinFETs in the die are equal to integer times of the minimum pitch.

5. The die of claim 4 , wherein all semiconductor fins of all FinFETs in the die have lengthwise directions parallel to the first direction, and wherein all pitches of all semiconductor fins of all FinFETs in the die are equal to integer times of the minimum pitch.

6. The die of claim 1 , wherein substantially no semiconductor fin of any FinFET in the die has a lengthwise direction parallel to a second direction perpendicular to the first direction.

7. The die of claim 1 , wherein the at least one standard cell is selected from the group consisting of an inverter, an NOR gate, an NAND gate, an XOR gate, and combinations thereof.

8. A die comprising:
a standard cell;
a macro comprising an analog macro, wherein the analog macro comprises an operational amplifier macro; and
a Fin Field-Effect Transistor (FinFET) in each of the standard cell and the macro, wherein substantially all semiconductor fins for forming all FinFETs in the die are parallel to a first direction, and wherein pitches of the all semiconductor fins are equal to integer times a minimum pitch among the pitches, and wherein the minimum pitch is a smallest pitch of the all pitches of the all semiconductor fins, and the pitches of the all semiconductor fins comprise a first pitch equal to the minimum pitch, and a second pitch greater than the minimum pitch.

9. The die of claim 8 , wherein the macro further comprises a memory macro, and wherein the memory macro comprises a Static Random Access Memory (SRAM) cell.

10. The die of claim 9 , wherein the memory macro comprises a first boundary and a second boundary parallel to the first direction, and wherein a distance between the first boundary and the second boundary is equal to integer times the minimum pitch.

11. The die of claim 8 , wherein the macro further comprises an IO macro, and wherein the IO macro comprises an Electro Static Discharge (ESD) macro.

12. The die of claim 8 , wherein substantially no semiconductor fin in the die has a lengthwise direction perpendicular to the first direction.

13. The die of claim 8 , wherein the integer times is greater than one time.

14. The die of claim 8 , wherein the standard cell is selected from the group consisting of an inverter, an NOR gate, an NAND gate, an XOR gate, and combinations thereof.

15. A method comprising:
placing a standard cell into a die representation, wherein the step of placing the standard cell is performed using a computer, wherein a first boundary and a second boundary of the standard cell are aligned to a first grid line and a second grid line, respectively, and wherein the grid is distributed throughout the die representation; and
placing a macro into the die representation, with the standard cell and the macro being different types of cells, wherein a third boundary and a fourth boundary of the macro are aligned to a third grid line and a fourth grid line, respectively, and wherein the first, the second, the third, and the fourth grid lines belong to grid lines of a grid have a uniform pitch, and wherein the macro is selected from a memory macro, an analog macro, an Input/output macro, and combinations thereof, wherein at least one of the placing the standard cell and the placing the macro is performed using a computer, wherein when a design of the die representation is finished, all fins of all FinFETs in the die representation are aligned to the grid lines, and first fins of the standard cell have a first pitch, and second fins of the macro have a second pitch, and a first one of the first pitch and the second pitch is greater than the uniform pitch, and a second one of the first pitch and the second pitch is equal to the uniform pitch.

16. The method of claim 15 , wherein after the steps of placing the standard cell and the macro, all fins of all Fin Field-Effect Transistors (FinFETs) in the standard cell and the macro are aligned to the grid lines.

17. The method of claim 15 , wherein the macro comprises a memory macro.

18. The method of claim 15 , wherein the macro comprises an analog macro.

19. The method of claim 15 , wherein the macro comprises an Input/output (JO) macro.

20. The method of claim 15 , when the design of the die representation is finished, all fins of all FinFETs in the die representation have lengthwise direction parallel to each other.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Yang Kuo-Nan
• Lin Chou-Kun
• Kao Jerry Chang-Jui
• Tsai Yi-Chuin
• Chao Chien-Ju
• Wang Chung-Hsing

Classifications

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H10F39/802

  Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes · CPC title

• H10D84/00 Primary

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title

• G06F17/5072 Primary

  Physics · mapped topic

• H10B12/056

  the transistor being a FinFET · CPC title