Forming a stress compensation layer and structures formed thereby

Patent metadata

Field	Value
Publication number	US-9929080-B2
Application number	US-99022804-A
Country	US
Kind code	B2
Filing date	Nov 15, 2004
Priority date	Nov 15, 2004
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

Methods of forming a microelectronic structure are described. Those methods comprise forming a stress compensation layer on a substrate, forming at least one opening within the stress compensation layer, and forming an interconnect paste within the at least one opening.

First claim

What is claimed is:

1. A method of forming a structure comprising;
forming a stress compensation layer directly on a package substrate, wherein the stress compensation layer comprises a no-flow underfill material;
forming at least one opening within the stress compensation layer with a microtool, the forming performed while the stress compensation layer is at a temperature between 80 to about 120 degrees Celsius to provide fluidity of the stress compensation layer during the forming of the at least one opening, wherein the at least one opening comprises a planar bottom surface and at least one sidewall, and wherein the at least one opening is formed to be in direct contact with the substrate;
forming an interconnect paste within the at least one opening, wherein the interconnect paste is in direct contact with the substrate; and
forming a solder ball from the interconnect paste in the at least one opening.

2. The method of claim 1 wherein forming a stress compensation layer on a substrate comprises: forming a stress compensation layer on a substrate; and removing moisture from the stress compensation layer, wherein the temperature of the moisture removal does not substantially cure the stress compensation layer.

3. The method of claim 1 further comprising heating the interconnect paste to form the solder ball.

4. The method of claim 3 wherein a height of the stress compensation layer is less than a height of the solder ball.

5. The method of claim 3 wherein heating the interconnect paste to form the solder ball comprises reflowing the interconnect structures at a temperature between about 230 degrees Celsius and 280 degrees Celsius.

6. The method of claim 3 wherein heating the interconnect paste to form the solder ball further comprises curing the stress compensation layer.

7. The method of claim 1 wherein forming at least one opening within the stress compensation layer further comprises exposing the at least one opening within the stress compensation layer to a cleaning process.

8. The method of claim 1 wherein forming an interconnect paste within the at least one opening comprises forming an interconnect paste within the at least one opening, wherein a height of the stress compensation layer is less than a height of the interconnect paste.

9. The method of claim 1 wherein forming an interconnect paste within the at least one opening, wherein the height of the stress compensation layer is less than the height of the interconnect paste comprises forming an interconnect paste within the at least one opening, wherein the height of the stress compensation layer is about 10 to about 60 percent of the height of the interconnect paste.

10. The method of claim 1 wherein forming the stress compensation layer comprises at forming at least one of epoxy, a cyanate ester, a polyimide, a polybenzoxazole, a polybenzimidazole, and a polybenzothiazole.

11. The method of claim 1 wherein forming the interconnect paste comprises forming a solder paste by at least one of stencil printing, solder jetting and solder mold transfer.

Assignees

• Suh Daewoong
• Jayaraman Saikumar
• Intel Corp

Inventors

• Suh Daewoong
• Jayaraman Saikumar

Classifications

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W74/012

  of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10W90/701 Primary

  characterised by the relative positions of pads or connectors relative to package parts · CPC title