Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates

Patent metadata

Field	Value
Publication number	US-9929063-B1
Application number	US-201715721762-A
Country	US
Kind code	B1
Filing date	Sep 30, 2017
Priority date	Apr 4, 2016
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

A process for making an integrated circuit, either in the form of a wafer, die, or chip, includes instantiating multiple standard cell-compatible fill cells, configured to enable non-contact electrical measurements. Such instantiated fill cells include mesh pads that contain at least three conductive stripes disposed between adjacent gate stripes. Such instantiated fill cells further include geometry to enable non-contact evaluation of Tip-to-Side shorts and/or leakages.

First claim

The invention claimed is:

1. A process for making an integrated circuit (IC) that includes a multiplicity of standard cell library compatible, non-contact electrical measurement (NCEM)-enabled fill cells, such process including instantiating each of said NCEM-enabled fills cells by:
patterning at least first and second power rails, each in a conductive layer, with each power rail extending longitudinally in a first direction and configured for abutted instantiation with logic cells in the standard cell library;
patterning a plurality of gate (GATE) stripes, with each extending longitudinally, in a second direction perpendicular to the first direction, from at least the first power rail to at least the second power rail, each of the GATE stripes having a uniform transverse thickness and a uniform center-to-center spacing (CPP) between adjacent GATE stripes;
instantiating an NCEM pad, by:
patterning at least three first-direction stripes, each in a conductive layer, each extending longitudinally in the first direction, and each positioned in a transverse direction between the first and second power rails;
patterning at least three second-direction stripes, each in a conductive layer, each extending longitudinally in the second direction, each positioned longitudinally between the first and second power rails, and each positioned transversely between adjacent GATE stripes, such that the center-to-center spacing between adjacent second-direction stripes is CPP;
connecting each of the first-direction stripes to each of the second-direction stripes;

instantiating at least one tip-to-side test area, by patterning a first feature and a second feature that is perpendicularly aligned with, but not electrically connected to, the first feature, the tip-to-side test area characterized by a gap dimension, defined by a spacing between an opposing end of the first feature and a side of the second feature, and a lateral dimension, defined by a common run length between the opposing end of the first feature and the side of the second feature; and,
patterning pad/ground wiring to (i) connect one of the first or second features to the NCEM pad and (ii) connect the other of the first or second features to at least one of power rails.

2. A process, as defined in claim 1 , wherein the process produces NCEM-enabled fill cells that are configured as tip-to-side-short-configured fill cells.

3. A process, as defined in claim 1 , wherein the process produces NCEM-enabled fill cells that are configured as tip-to-side-leakage-configured fill cells.

4. A process, as defined in claim 1 , wherein instantiating the NCEM pad includes patterning four first-direction stripes, each in a conductive layer, each extending longitudinally in the first direction, and each positioned in the transverse direction between the first and second power rails.

5. A process, as defined in claim 1 , that includes single patterning the first-direction stripes.

6. A process, as defined in claim 1 , that includes double patterning the first-direction stripes.

7. A process, as defined in claim 1 , that includes triple patterning the first-direction stripes.

8. A process, as defined in claim 1 , that includes single patterning the second-direction stripes.

9. A process, as defined in claim 1 , that includes double patterning the second-direction stripes.

10. A process, as defined in claim 1 , that includes triple patterning the second-direction stripes.

11. A process, as defined in claim 1 , wherein instantiating the NCEM-enabled fill cells includes instantiating at least two tip-to-side test areas, wired in parallel.

12. A process, as defined in claim 11 , wherein each of the parallel-wired tip-to-side test areas is identically configured.

13. A process, as defined in claim 1 , wherein the process produces an IC in the form of a semiconductor wafer.

14. A process, as defined in claim 1 , wherein the process produces an IC in the form of a semiconductor die.

15. A process, as defined in claim 1 , wherein the process produces an IC in the form of a packaged semiconductor chip.

16. A process, as defined in claim 1 , wherein the NCEM-enabled fill cells form a design of experiments (DOE) in which some of the NCEM-enabled fill cells differ in terms of the gap dimension of their respective tip-to-side test area(s).

17. A process, as defined in claim 1 , wherein the NCEM-enabled fill cells form a design of experiments (DOE) in which some of the NCEM-enabled fill cells differ in terms of the lateral dimension of their respective tip-to-side test area(s).

18. A process, as defined in claim 1 , wherein the NCEM-enabled fill cells form a design of experiments (DOE) in which some of the NCEM-enabled fill cells differ in terms of other patterning within expanded test area(s) that surround the tip-to-side test area(s).

19. A process, as defined in claim 1 , that further comprises instantiating additional, differently configured, NCEM-enabled fill cells, said differently configured fill cells selected from a list that consists of:
tip-to-tip-short-configured, NCEM-enabled fill cells;
tip-to-tip-leakage-configured, NCEM-enabled fill cells;
tip-to-side-short-configured, NCEM-enabled fill cells;
tip-to-side-leakage-configured, NCEM-enabled fill cells;
side-to-side-short-configured, NCEM-enabled fill cells;
side-to-side-leakage-configured, NCEM-enabled fill cells;
L-shape-interlayer-short-configured, NCEM-enabled fill cells;
L-shape-interlayer-leakage-configured, NCEM-enabled fill cells;
diagonal-short-configured, NCEM-enabled fill cells;
diagonal-leakage-configured, NCEM-enabled fill cells;
corner-short-configured, NCEM-enabled fill cells;
corner-leakage-configured, NCEM-enabled fill cells;
interlayer-overlap-short-configured, NCEM-enabled fill cells;
interlayer-overlap-leakage-configured, NCEM-enabled fill cells;
via-chamfer-short-configured, NCEM-enabled fill cells;
via-chamfer-leakage-configured, NCEM-enabled fill cells;
merged-via-short-configured, NCEM-enabled fill cells;
merged-via-leakage-configured, NCEM-enabled fill cells;
snake-open-configured, NCEM-enabled fill cells;
snake-resistance-configured, NCEM-enabled fill cells;
stitch-open-configured, NCEM-enabled fill cells;
stitch-resistance-configured, NCEM-enabled fill cells;
via-open-configured, NCEM-enabled fill cells;
via-resistance-configured, NCEM-enabled fill cells;
metal-island-open-configured, NCEM-enabled fill cells;
metal-island-resistance-configured, NCEM-enabled fill cells;
merged-via-open-configured, NCEM-enabled fill cells; and,
merged-via-resistance-configured, NCEM-enabled fill cells.

Assignees

• Pdf Solutions Inc

Inventors

• Lam Stephen
• Ciplickas Dennis
• Brozek Tomasz
• Cheng Jeremy
• Comensoli Simone
• De Indranil
• Doong Kelvin
• Eisenmann Hans
• Fiscus Timothy
• Haigh Jonathan
• Hess Christopher
• Kibarian John
• Lee Sherry
• Liao Marci
• Lin Sheng-Che
• Matsuhashi Hideki
• Michaels Kimon
• O'Sullivan Conor
• Rauscher Markus
• Rovner Vyacheslav
• Strojwas Andrzej
• Strojwas Marcin
• Taylor Carl
• Vallishayee Rakesh
• Weiland Larg
• Yokoyama Nobuharu

Classifications

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F11/079

  Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/30

  Circuit design · CPC title

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title