Method of manufacturing semiconductor package

Patent metadata

Field	Value
Publication number	US-9922897-B1
Application number	US-201715481446-A
Country	US
Kind code	B1
Filing date	Apr 6, 2017
Priority date	Sep 13, 2016
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

A method of manufacturing a semiconductor package includes forming a preliminary package, on a supporting substrate, which includes a connection substrate, a semiconductor chip and a molding pattern on the connection substrate and the semiconductor chip, forming a buffer pattern on the molding pattern, and forming a carrier substrate, on the buffer pattern, which includes a first portion contacting the buffer pattern and a second portion contacting the molding pattern.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor package, the method comprising:
forming a preliminary package on a supporting substrate, the preliminary package including a connection substrate, a semiconductor chip and a molding pattern on the connection substrate and the semiconductor chip;
forming a buffer pattern on the molding pattern; and
forming a carrier substrate on the buffer pattern and the molding pattern, the carrier substrate including a first portion contacting the buffer pattern and a second portion contacting the molding pattern.

2. The method according to claim 1 , wherein the buffer pattern includes a non-adhesive material.

3. The method according to claim 1 , further comprising removing the carrier substrate,
wherein removing the carrier substrate includes:
a first removing process of removing the second portion of the carrier substrate by performing a sawing process on the carrier substrate: and
a second removing process of separating the carrier substrate from the buffer pattern.

4. The method according to claim 3 , further comprising:
removing the supporting substrate to expose a lower surface of the preliminary package; and
forming a redistribution substrate on the lower surface of the preliminary package,
wherein removing the carrier substrate is performed after forming the redistribution substrate.

5. The method according to claim 4 , wherein the redistribution substrate includes insulating patterns and a redistribution pattern.

6. The method according to claim 5 , wherein the redistribution pattern is electrically connected to the semiconductor chip and the connection substrate.

7. The method according to claim 1 , wherein the second portion of the carrier substrate is overlapped with an edge region of the preliminary package in plan view.

8. A method of manufacturing a semiconductor package, the method comprising:
providing a preliminary package, the preliminary package including a connection substrate, a semiconductor chip and a molding pattern;
providing a buffer pattern on a first portion of the molding pattern, the buffer pattern exposing an upper surface of a second portion of the molding pattern;
providing a carrier substrate on the buffer pattern and the molding pattern, the carrier substrate contacting the upper surface of the second portion of the molding pattern; and
removing the second portion of the molding pattern to detach the carrier substrate from the molding pattern.

9. The method according to claim 8 , wherein the carrier substrate is attached to the preliminary package by the second portion of the molding pattern.

10. The method according to claim 8 , further comprising, after detaching the carrier substrate, removing the carrier substrate from the preliminary package.

11. The method according to claim 10 , further comprising, after removing the carrier substrate, disposing an upper package on the molding pattern,
wherein the connection substrate includes a base layer and a conductive member in the base layer, and
wherein the upper package is electrically connected to the conductive member.

12. The method according to claim 8 , wherein the second portion of the molding pattern is provided in an edge region of the preliminary package.

13. The method according to claim 8 , wherein removing the second portion of the molding pattern includes sawing the carrier substrate and the preliminary package to separate the second portion of the molding pattern from the first portion of the molding pattern.

14. The method according to claim 8 , wherein removing the second portion of the molding pattern includes chemically etching a sidewall of the preliminary package.

15. The method according to claim 8 , wherein after providing the carrier substrate, the upper surface of the second portion of the molding pattern is substantially coplanar with an upper surface of the buffer pattern.

16. A method of manufacturing a semiconductor package, the method comprising:
forming a package on a supporting substrate, the package including a connection substrate including openings exposing the supporting substrate, semiconductor chips in respective ones of the openings and a molding pattern covering the supporting substrate and the semiconductor chips;
forming a buffer pattern on the package, the buffer pattern exposing the molding pattern; and
forming a carrier substrate on the buffer pattern and the molding pattern, the carrier substrate contacting an upper surface of the buffer pattern and an upper surface of the exposed molding pattern.

17. The method according to claim 16 , wherein the buffer pattern includes a non-adhesive material.

18. The method according to claim 16 , wherein the buffer pattern includes a plurality of buffer patterns spaced apart from each other, and
wherein the molding pattern is present in a gap between the buffer patterns.

19. The method according to claim 16 , further comprising forming a substrate on a lower surface of the package,
wherein the substrate includes first regions overlapped with the semiconductor chips, respectively, when viewed in plan view, and a dummy region between the first regions, and
wherein a test pad and/or an alignment key is formed in the dummy region of the substrate.

20. The method according to claim 16 , wherein the carrier substrate contacts the molding pattern in an edge region of the package.

Assignees

• Kim Kyoung Hwan
• Kang Taewoo
• Park Byung Lyul
• Jeon Hyungjun
• Samsung Electronics Co Ltd

Inventors

• Kim Kyoung Hwan
• Kang Taewoo
• Park Byung Lyul
• Jeon Hyungjun

Classifications

• H10P72/7436

  used to support a device or a wafer when forming electrical connections thereto · CPC title

• H10P72/7424

  used as a support during the manufacture of self-supporting substrates · CPC title

• H10P72/7412

  the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support · CPC title

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10P72/743

  used as a support during manufacture of interconnect decals or build up layers · CPC title