Source down semiconductor devices and methods of formation thereof

Patent metadata

Field	Value
Publication number	US-9911686-B2
Application number	US-201615155271-A
Country	US
Kind code	B2
Filing date	May 16, 2016
Priority date	Aug 4, 2014
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

A method for forming a semiconductor device includes forming device regions in a semiconductor substrate having a first side and a second side. The device regions are formed adjacent the first side. The method further includes forming a seed layer over the first side of the semiconductor substrate, and forming a patterned resist layer over the seed layer. A contact pad is formed over the seed layer within the patterned resist layer. The method further includes removing the patterned resist layer after forming the contact pad to expose a portion of the seed layer underlying the patterned resist layer, and forming a protective layer over the exposed portion of the seed layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a chip comprising
a diced semiconductor substrate comprising a gate region and a drain region at a first major surface and a source region at a second major surface opposite to the first major surface,
a seed layer disposed over and overlapping with all of the second major surface of the diced semiconductor substrate,
a barrier layer disposed between the seed layer and the second major surface of the diced semiconductor substrate, the barrier layer coupled to the source region,
a patterned contact pad disposed over and covering a portion of the seed layer,
an insulating liner disposed around sidewalls of the patterned contact pad and extending over a part of the seed layer, and
a diced carrier material disposed at the sidewalls of the patterned contact pad over the insulating liner.

2. The device of claim 1 , wherein the diced carrier comprises a sintered ceramic material.

3. The device of claim 2 , wherein the sintered ceramic material comprises silicon oxide, alumina, magnesium oxide, titanium oxide, and polymer filled organic compound materials.

4. The device of claim 2 , further comprising:
a die paddle, wherein the contact pad is disposed on the die paddle, wherein the contact pad is disposed between the diced semiconductor substrate and the die paddle;
a first interconnect coupling a first lead with a first back side contact of the diced semiconductor substrate; and
a second interconnect coupling a second lead with a second back side contact of the diced semiconductor substrate.

5. The device of claim 4 , wherein the contact pad is a common source contact.

6. A semiconductor device comprising:
a chip comprising
a diced semiconductor substrate comprising a gate region and a drain region at a first major surface and a source region at a second major surface opposite to the first major surface,
a titanium tungsten layer covering all of the second major surface of the diced semiconductor substrate,
a barrier layer disposed between the titanium tungsten layer and the second major surface of the diced semiconductor substrate, the barrier layer coupled to the source region,
a copper pad disposed over and covering a portion of the titanium tungsten layer, and
an insulating liner disposed around sidewalls of the copper pad and extending over a part of the titanium tungsten layer, and
a diced ceramic carrier material surrounding sidewalls of the copper pad.

7. The device of claim 6 , wherein the diced ceramic carrier material comprises a sintered ceramic material.

8. The device of claim 7 , wherein the sintered ceramic material comprises silicon oxide, alumina, magnesium oxide, titanium oxide, and polymer filled organic compound materials.

9. The device of claim 6 , further comprising:
a die paddle, wherein the copper pad is disposed on the die paddle, wherein the copper pad is disposed between the diced semiconductor substrate and the die paddle;
a first bond wire coupling a first lead with a first back side contact of the diced semiconductor substrate; and
a second bond wire coupling a second lead with a second back side contact of the diced semiconductor substrate.

10. The device of claim 9 , wherein the first bond wire and the second bond wire comprise copper wires.

11. The device of claim 6 , wherein the diced carrier material is thicker than the diced semiconductor substrate.

12. An assembled semiconductor device comprising:
a chip disposed over a die paddle, the chip comprising
a diced semiconductor substrate comprising a source, a drain, and a gate, the source disposed at a first major surface of the diced semiconductor substrate and the gate and the drain disposed at a second major surface of the diced semiconductor substrate, wherein the first major surface is opposite to the second major surface,
a barrier layer covering all of the first major surface;
a seed layer disposed over the barrier layer,
a patterned contact pad disposed over and covering a portion of the seed layer, wherein the patterned contact pad is attached to the die paddle and the second major surface faces away from the die paddle, and
a diced carrier material surrounding sidewalls of the patterned contact pad.

13. The device of claim 12 , wherein the diced carrier material comprises a sintered ceramic material.

14. The device of claim 13 , wherein the sintered ceramic material comprises silicon oxide, alumina, magnesium oxide, titanium oxide, and polymer filled organic compound materials.

15. The device of claim 12 , further comprising:
a first interconnect coupling a first lead with the gate; and
a second interconnect coupling a second lead with the drain.

16. The device of claim 15 , wherein the first interconnect and the second interconnect comprise copper wires.

17. The device of claim 12 , wherein the barrier layer comprises titanium tungsten, the seed layer comprises copper, and the patterned contact pad comprises copper.

18. The device of claim 12 , wherein the patterned contact pad is thicker than the diced semiconductor substrate.

19. The device of claim 12 , wherein the diced carrier material is thicker than the diced semiconductor substrate.

20. The device of claim 12 , wherein the barrier layer is disposed between the seed layer and the diced semiconductor substrate.

Assignees

• Infineon Technologies Ag

Inventors

• Schneegans Manfred
• Meiser Andreas
• Mischitz Martin
• Roesner Michael
• Pinczolits Michael

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title