Semiconductor device and method for fabricating a semiconductor device

Patent metadata

Field	Value
Publication number	US-9502421-B2
Application number	US-201414574982-A
Country	US
Kind code	B2
Filing date	Dec 18, 2014
Priority date	Mar 6, 2012
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A semiconductor device is disclosed. In one embodiment, the semiconductor device includes two different semiconductor materials. The two semiconductor materials are arranged adjacent one another in a common plane.

First claim

What is claimed is:

1. A method, comprising:
providing a substrate having a surface capable of sustaining epitaxial growth of a III-V semiconductor;
applying a <100> silicon layer to the substrate;
removing portions of the <100> silicon layer and revealing the surface of the substrate in a first region and producing a second region comprising <100> silicon;
epitaxially growing a III-V semiconductor on the surface of the substrate in the first region;
fabricating a HEMT structure in the first region;
fabricating a CMOS device in the second region;
depositing a dielectric layer over the first region and the second region;
removing portions of the dielectric layer positioned over the first region and the second region and producing through holes exposing contact regions of the first region and the second region;
depositing an electrically conductive material in the through holes;
depositing an electrically conductive material onto the dielectric layer and the electrically conductive material in the through holes; and
removing portions of the substrate under the first region and exposing the III-V semiconductor.

2. A method, comprising:
providing a substrate having a surface capable of sustaining epitaxial growth of a III-V semiconductor;
applying a <100> silicon layer to the substrate;
removing portions of the <100> silicon layer and revealing the surface of the substrate in a first region and producing a second region comprising <100> silicon;
epitaxially growing a III-V semiconductor on the surface of the substrate in the first region;
fabricating a HEMT structure in the first region;
fabricating a CMOS device in the second region;
depositing a dielectric layer over the first region and the second region;
removing portions of the dielectric layer positioned over the first region and the second region and producing through holes exposing contact regions of the first region and the second region;
depositing an electrically conductive material in the through holes;

depositing an electrically conductive material onto the dielectric layer and the electrically conductive material in the through holes; and
applying dielectric material onto the exposed III-V semiconductor.

3. A method, comprising:
providing a substrate having a surface capable of sustaining epitaxial growth of a III-V semiconductor;
applying a <100> silicon layer to the substrate;
removing portions of the <100> silicon layer and revealing the surface of the substrate in a first region and producing a second region comprising <100> silicon;
epitaxially growing a III-V semiconductor on the surface of the substrate in the first region;
fabricating a HEMT structure in the first region;
fabricating a CMOS device in the second region;
depositing a dielectric layer over the first region and the second region;
removing portions of the dielectric layer positioned over the first region and the second region and producing through holes exposing contact regions of the first region and the second region;
depositing an electrically conductive material in the through holes;

depositing an electrically conductive material onto the dielectric layer and the electrically conductive material in the through holes; and
removing the substrate and applying an insulating layer to the rear of the first region and the rear of the second region.

4. A method, comprising:
providing a substrate having a surface capable of sustaining epitaxial growth of a III-V semiconductor;
applying a <100> silicon layer to the substrate;
removing portions of the <100> silicon layer and revealing the surface of the substrate in a first region and producing a second region comprising <100> silicon;
epitaxially growing a III-V semiconductor on the surface of the substrate in the first region;
fabricating a HEMT structure in the first region;
fabricating a CMOS device in the second region;
depositing a dielectric layer over the first region and the second region;
removing portions of the dielectric layer positioned over the first region and the second region and producing through holes exposing contact regions of the first region and the second region;
depositing an electrically conductive material in the through holes; and

depositing an electrically conductive material onto the dielectric layer and the electrically conductive material in the through holes; and
removing portions of the <100> silicon to produce a trench structure, and depositing a dielectric layer in the trenches.

5. A method, comprising:
providing a substrate having a surface capable of sustaining epitaxial growth of a III-V semiconductor;
applying a <100> silicon layer to the substrate;
removing portions of the <100> silicon layer and revealing the surface of the substrate in a first region and producing a second region comprising <100> silicon;
epitaxially growing a III-V semiconductor on the surface of the substrate in the first region;
fabricating a HEMT structure in the first region;
fabricating a CMOS device in the second region;
depositing a dielectric layer over the first region and the second region;
removing portions of the dielectric layer positioned over the first region and the second region and producing through holes exposing contact regions of the first region and the second region;
depositing an electrically conductive material in the through holes; and

depositing an electrically conductive material onto the dielectric layer and the electrically conductive material in the through holes; and
providing a <111> silicon wafer as the substrate and bonding it to a <100> silicon wafer with an intermediate oxide layer.

6. The method according to claim 5 , further comprising implanting ions into a peripheral region of the first region.

7. The method according to claim 5 , further comprising applying an oxide layer on the surface of the <100> silicon of the second region, depositing a nitride layer on the oxide layer and removing the <100> silicon in the first region.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Hirler Franz
• Meiser Andreas

Classifications

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title