Semiconductor structure and method for making same

Patent metadata

Field	Value
Publication number	US-9230885-B2
Application number	US-201314060641-A
Country	US
Kind code	B2
Filing date	Oct 23, 2013
Priority date	Sep 30, 2010
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

One or more embodiments relate to a method for forming a semiconductor structure, comprising: providing a workpiece; forming a dielectric barrier layer over the workpiece; forming an opening through the dielectric barrier layer; forming a seed layer over the dielectric barrier layer and within the dielectric barrier layer opening; and electroplating a first fill layer on the seed layer.

First claim

What is claimed is:

1. A method for forming a semiconductor structure, comprising:
providing a workpiece comprising a first opening;
forming a dielectric barrier layer over said workpiece, the dielectric barrier layer lining the first opening;
forming a second opening through said dielectric barrier layer, wherein forming the second opening exposes additional sidewalls of the dielectric barrier layer, wherein a first distance between opposite sidewalls of the dielectric barrier layer in the first opening is greater than a second distance between opposite additional sidewalls of the dielectric barrier layer;
forming a seed layer in direct contact with said dielectric barrier layer and within said second opening;
forming a photoresist layer over said seed layer;
forming a third opening through said photoresist layer to expose said seed layer;
electroplating a first fill layer on said seed layer; and
removing said photoresist layer after said electroplating.

2. The method of claim 1 , further comprising electroplating a second fill layer on said first fill layer.

3. The method of claim 1 , wherein said first fill layer and/or said seed layer comprises Cu (copper).

4. The method of claim 1 , wherein said dielectric barrier layer comprises an oxide, a nitride and/or an oxynitride.

5. The method of claim 2 , wherein said second fill layer comprises Cu (copper).

6. The method of claim 1 , wherein forming said second opening through said dielectric barrier layer includes forming a first photoresist over said dielectric barrier layer and forming an opening through said first photoresist.

7. The method of claim 1 , wherein said workpiece includes a conductive region, said forming said second opening through said dielectric barrier layer includes exposing said conductive region.

8. The method of claim 7 , wherein said seed layer is in direct contact with said conductive region.

9. A method of forming a semiconductor structure, comprising:
providing a dielectric layer;
forming a first opening in said dielectric layer, said first opening including at least one sidewall surface and a bottom surface;
forming a dielectric barrier layer in direct contact with said at least one sidewall surface and said bottom surface;
forming a second opening through said dielectric barrier layer, exposing said bottom surface, wherein said dielectric barrier layer within the first opening comprises a vertical portion and a horizontal portion after forming the second opening;
forming a seed layer in direct contact with said dielectric barrier layer and within said second opening;
forming a photoresist layer over said seed layer;
forming a third opening through said photoresist layer to expose said seed layer;
electroplating a fill layer on said seed layer; and
removing said photoresist layer after said electroplating.

10. The method of claim 9 , wherein said fill layer and/or said seed layer comprises Cu (copper).

11. The method of claim 9 , wherein said dielectric barrier layer comprises an oxide, a nitride and/or an oxynitride.

12. The method of claim 9 , wherein said bottom surface of said second opening in said dielectric barrier layer includes a surface of a conductive region.

13. The method of claim 9 , wherein the seed layer within the first opening comprises a first horizontal portion disposed over the horizontal portion of said dielectric barrier layer and a second horizontal portion centrally located in the first opening, wherein the first horizontal portion and the second horizontal portion have different top surfaces.

14. The method of claim 9 , wherein the first opening comprises a first trench and the second opening comprises a second trench.

15. The method of claim 9 , wherein the first opening comprises a first hole and the second opening comprises a second hole.

Assignees

• Infineon Technologies Ag

Inventors

• Meinhold Dirk
• Dallmann Gerald
• Vater Alfred

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/076 Primary

  in via holes or trenches · CPC title

• H10W20/063

  by forming conductive members before forming protective insulating material · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/01

  Manufacture or treatment · CPC title