Semiconductor package with integrated output inductor on a printed circuit board

Patent metadata

Field	Value
Publication number	US-9911679-B2
Application number	US-201715425614-A
Country	US
Kind code	B2
Filing date	Feb 6, 2017
Priority date	Mar 25, 2015
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

A semiconductor package includes a semiconductor die comprising a control transistor and a sync transistor, an integrated output inductor comprising a winding around a core, and coupled to the semiconductor die. The winding comprises a plurality of conductive clips situated above a printed circuit board (PCB) and connected to a plurality of conductive segments in the PCB. The control transistor and the sync transistor are configured as a half-bridge. The integrated output inductor is coupled to a switched node of the half-bridge. At least one of the plurality of conductive clips includes a partially etched portion and a non-etched portion. The semiconductor die is attached to the integrated output inductor by a die attach material. The semiconductor die and the integrated output inductor are encapsulated in a molding compound.

First claim

The invention claimed is:

1. A semiconductor package comprising:
a core of an output inductor;
a plurality of discrete conductive clips of the output inductor each situated over and in contact with the core of the output inductor; and
a semiconductor die situated over the plurality of discrete conductive clips;
wherein each one of the plurality of discrete conductive clips comprises a first segment and a second segment that each extend away from a third segment to bridge the core of the output inductor so that the plurality of discrete conductive clips together form a first half of a winding of the output inductor external a printed circuit board and so that the plurality of discrete conductive clips are configured to be connected to corresponding conductive segments in the printed circuit board that together form a second half of the winding of the output inductor.

2. The semiconductor package of claim 1 wherein the semiconductor die comprises a control transistor and a sync transistor configured as a half-bridge.

3. The semiconductor package of claim 2 wherein the semiconductor die further comprises a driver integrated circuit coupled to the control transistor and the sync transistor.

4. The semiconductor package of claim 2 wherein at least one of the control transistor and the sync transistor comprises a group III-V transistor.

5. The semiconductor package of claim 2 wherein at least one of the control transistor and the sync transistor comprises a group IV transistor.

6. The semiconductor package of claim 2 wherein the plurality of discrete conductive clips are configured to be electrically coupled to a switched node of the half-bridge.

7. The semiconductor package of claim 1 wherein at least one of the plurality of discrete conductive clips includes an etched portion and a non-etched portion.

8. The semiconductor package of claim 1 wherein the core is a ferrite core.

9. The semiconductor package of claim 1 wherein the semiconductor die is coupled to the plurality of discrete conductive clips by a die attach material.

10. The semiconductor package of claim 1 wherein the core, the plurality of discrete conductive clips and the semiconductor die are encapsulated in a molding compound.

11. A semiconductor package comprising:
a stack comprising a core of an output inductor, a plurality of conductive clips of the output inductor, and a power stage;
wherein each one of the plurality of conductive clips comprises a first segment, a second segment and a third segment, wherein the first segment and second segment each extend away from the third segment to bridge the core of the output inductor so that the plurality of conductive clips together define a first half of a winding of the output inductor external a printed circuit board and so that the plurality of conductive clips are configured to be connected to corresponding conductive segments in the printed circuit board that together define a second half of the winding of the output inductor when coupled to corresponding ones of the plurality of conductive clips.

12. The semiconductor package of claim 11 wherein at least one of the plurality of conductive clips includes an etched portion and a non-etched portion.

13. The semiconductor package of claim 11 wherein the plurality of conductive clips are configured to be electrically coupled to a switched node of a half-bridge defined by a control transistor and a sync transistor of the power stage.

14. The semiconductor package of claim 13 wherein the power stage further comprises a driver integrated circuit coupled to the control transistor and the sync transistor.

15. The semiconductor package of claim 13 wherein at least one of the control transistor and the sync transistor comprises a group III-V transistor.

16. The semiconductor package of claim 13 wherein at least one of the control transistor and the sync transistor comprises a group IV transistor.

17. The semiconductor package of claim 13 wherein the control transistor and the sync transistor are monolithically integrated on a semiconductor die.

18. The semiconductor package of claim 17 wherein the semiconductor die is attached to the plurality of conductive clips by a die attach material.

19. The semiconductor package of claim 11 wherein the stack is encapsulated in a molding compound.

20. The semiconductor package of claim 11 wherein the core is a ferrite core.

Assignees

• Infineon Techonologies Americas Corp
• Infineon Technologies Americas Corp

Inventors

• Cho Eung San

Classifications

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/738

  between a chip and a stacked discrete passive device · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title