Integrated III-Nitride D-Mode HFET with Cascoded Pair Half Bridge
US-2015014698-A1 · Jan 15, 2015 · US
US9437570B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9437570-B2 |
| Application number | US-201414538483-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 11, 2014 |
| Priority date | Dec 5, 2013 |
| Publication date | Sep 6, 2016 |
| Grant date | Sep 6, 2016 |
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In one implementation, a power semiconductor package includes a conductive carrier including a switch node segment and a power output segment. The power semiconductor package also includes an integrated output inductor stacked over the conductive carrier and configured to couple the switch node segment to the power output segment. The power semiconductor package further includes a power stage stacked over the integrated output inductor.
Opening claim text (preview).
The invention claimed is: 1. A power semiconductor package comprising: a conductive carrier including a switch node segment and a power output segment; an integrated output inductor stacked over said conductive carrier and configured to couple said switch node segment to said power output segment; a power stage stacked over said integrated output inductor. 2. The power semiconductor package of claim 1 , wherein said integrated output inductor includes a switch node terminal coupled to a first end of a winding in said integrated output inductor, said switch node terminal situated over and coupled to said switch node segment. 3. The power semiconductor package of claim 1 , wherein said integrated output inductor includes a power output terminal coupled to a second end of said winding in said integrated output inductor, said power output terminal situated over and coupled to said power output segment. 4. The power semiconductor package of claim 1 , wherein said power stage is coupled to a switch node terminal of said integrated output inductor by a first wire bond connected to said switch node segment. 5. The power semiconductor package of claim 1 , wherein said power stage is further coupled to a power input terminal of said power semiconductor package by a second wire bond connected to a power input segment of said conductive carrier. 6. The power semiconductor package of claim 1 , wherein said power stage includes at least one group III-V power transistor. 7. The power semiconductor package of claim 1 , wherein said power stage includes at least one GaN power transistor. 8. The power semiconductor package of claim 1 , wherein said power stage is coupled to said integrated output inductor using a die attach material. 9. A power semiconductor package comprising: a conductive carrier including a switch node segment and a power output segment; an integrated output inductor stacked over said conductive carrier; said integrated output inductor having a switch node terminal coupled to a first end of a winding in said integrated output inductor, said switch node terminal situated over and coupled to said switch node segment; said integrated output inductor having a power output terminal coupled to a second end of said winding in said integrated output inductor, said power output terminal situated over and coupled to said power output segment; a power stage stacked over said integrated output inductor. 10. The power semiconductor package of claim 9 , wherein said power stage is coupled to a switch node terminal of said integrated output inductor by a first wire bond connected to said switch node segment. 11. The power semiconductor package of claim 9 , wherein said power stage is further coupled to a power input terminal of said power semiconductor package by a second wire bond connected to a power input segment of said conductive carrier. 12. The power semiconductor package of claim 9 , wherein said power stage includes at least one group III-V power transistor. 13. The power semiconductor package of claim 9 , wherein said power stage includes at least one GaN power transistor. 14. The power semiconductor package of claim 9 , wherein said power stage is coupled to said integrated output inductor using a die attach material. 15. A power semiconductor package comprising: a conductive carrier including a switch node segment and a power output segment; an integrated output inductor stacked over said conductive carrier and configured to couple said switch node segment to said power output segment; a power stage stacked over said integrated output inductor; said power stage being coupled to a switch node terminal of said integrated output inductor by a first wire bond connected to said switch node segment; said power stage being further coupled to a power input terminal of said power semiconductor package by a second wire bond connected to a power input segment of said conductive carrier. 16. The power semiconductor package of claim 15 , wherein said integrated output inductor includes a switch node terminal coupled to a first end of a winding in said integrated output inductor, said switch node terminal situated over and coupled to said switch node segment. 17. The power semiconductor package of claim 15 , wherein said integrated output inductor includes a power output terminal coupled to a second end of a winding in said integrated output inductor, said power output terminal situated over and coupled to said power output segment. 18. The power semiconductor package of claim 15 , wherein said power stage includes at least one group III-V power transistor. 19. The power semiconductor package of claim 15 , wherein said power stage includes at least one GaN power transistor. 20. The power semiconductor package of claim 15 , wherein said power stage is coupled to said integrated output inductor using a die attach material.
being rectangular · CPC title
comprising aluminium [Al] · CPC title
comprising gold [Au] · CPC title
Encapsulations, e.g. protective coatings · CPC title
Die-attach connectors and bond wires · CPC title
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