Power converter package with an integrated output inductor

US9437570B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9437570-B2
Application numberUS-201414538483-A
CountryUS
Kind codeB2
Filing dateNov 11, 2014
Priority dateDec 5, 2013
Publication dateSep 6, 2016
Grant dateSep 6, 2016

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

In one implementation, a power semiconductor package includes a conductive carrier including a switch node segment and a power output segment. The power semiconductor package also includes an integrated output inductor stacked over the conductive carrier and configured to couple the switch node segment to the power output segment. The power semiconductor package further includes a power stage stacked over the integrated output inductor.

First claim

Opening claim text (preview).

The invention claimed is: 1. A power semiconductor package comprising: a conductive carrier including a switch node segment and a power output segment; an integrated output inductor stacked over said conductive carrier and configured to couple said switch node segment to said power output segment; a power stage stacked over said integrated output inductor. 2. The power semiconductor package of claim 1 , wherein said integrated output inductor includes a switch node terminal coupled to a first end of a winding in said integrated output inductor, said switch node terminal situated over and coupled to said switch node segment. 3. The power semiconductor package of claim 1 , wherein said integrated output inductor includes a power output terminal coupled to a second end of said winding in said integrated output inductor, said power output terminal situated over and coupled to said power output segment. 4. The power semiconductor package of claim 1 , wherein said power stage is coupled to a switch node terminal of said integrated output inductor by a first wire bond connected to said switch node segment. 5. The power semiconductor package of claim 1 , wherein said power stage is further coupled to a power input terminal of said power semiconductor package by a second wire bond connected to a power input segment of said conductive carrier. 6. The power semiconductor package of claim 1 , wherein said power stage includes at least one group III-V power transistor. 7. The power semiconductor package of claim 1 , wherein said power stage includes at least one GaN power transistor. 8. The power semiconductor package of claim 1 , wherein said power stage is coupled to said integrated output inductor using a die attach material. 9. A power semiconductor package comprising: a conductive carrier including a switch node segment and a power output segment; an integrated output inductor stacked over said conductive carrier; said integrated output inductor having a switch node terminal coupled to a first end of a winding in said integrated output inductor, said switch node terminal situated over and coupled to said switch node segment; said integrated output inductor having a power output terminal coupled to a second end of said winding in said integrated output inductor, said power output terminal situated over and coupled to said power output segment; a power stage stacked over said integrated output inductor. 10. The power semiconductor package of claim 9 , wherein said power stage is coupled to a switch node terminal of said integrated output inductor by a first wire bond connected to said switch node segment. 11. The power semiconductor package of claim 9 , wherein said power stage is further coupled to a power input terminal of said power semiconductor package by a second wire bond connected to a power input segment of said conductive carrier. 12. The power semiconductor package of claim 9 , wherein said power stage includes at least one group III-V power transistor. 13. The power semiconductor package of claim 9 , wherein said power stage includes at least one GaN power transistor. 14. The power semiconductor package of claim 9 , wherein said power stage is coupled to said integrated output inductor using a die attach material. 15. A power semiconductor package comprising: a conductive carrier including a switch node segment and a power output segment; an integrated output inductor stacked over said conductive carrier and configured to couple said switch node segment to said power output segment; a power stage stacked over said integrated output inductor; said power stage being coupled to a switch node terminal of said integrated output inductor by a first wire bond connected to said switch node segment; said power stage being further coupled to a power input terminal of said power semiconductor package by a second wire bond connected to a power input segment of said conductive carrier. 16. The power semiconductor package of claim 15 , wherein said integrated output inductor includes a switch node terminal coupled to a first end of a winding in said integrated output inductor, said switch node terminal situated over and coupled to said switch node segment. 17. The power semiconductor package of claim 15 , wherein said integrated output inductor includes a power output terminal coupled to a second end of a winding in said integrated output inductor, said power output terminal situated over and coupled to said power output segment. 18. The power semiconductor package of claim 15 , wherein said power stage includes at least one group III-V power transistor. 19. The power semiconductor package of claim 15 , wherein said power stage includes at least one GaN power transistor. 20. The power semiconductor package of claim 15 , wherein said power stage is coupled to said integrated output inductor using a die attach material.

Assignees

Inventors

Classifications

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9437570B2 cover?
In one implementation, a power semiconductor package includes a conductive carrier including a switch node segment and a power output segment. The power semiconductor package also includes an integrated output inductor stacked over the conductive carrier and configured to couple the switch node segment to the power output segment. The power semiconductor package further includes a power stage s…
Who is the assignee on this patent?
Infineon Technologies Americas Corp, Infineon Technologies Americas Corp
What technology area does this patent fall under?
Primary CPC classification H10W70/40. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 06 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).