Power Converter Package with Integrated Output Inductor

Patent metadata

Field	Value
Publication number	US-2016104665-A1
Application number	US-201514855665-A
Country	US
Kind code	A1
Filing date	Sep 16, 2015
Priority date	Oct 8, 2014
Publication date	Apr 14, 2016
Grant date	—

Abstract

In one implementation, a semiconductor package includes a first patterned conductive carrier including partially etched segments. The semiconductor package also includes a control FET having a control drain attached to a first partially etched segment of the first patterned conductive carrier. In addition, the semiconductor package includes a sync FET having a sync source and a sync gate attached to respective second and third partially etched segments of the first patterned conductive carrier. The semiconductor package further includes a second patterned conductive carrier having a switch node segment situated over a control source of the control FET and over a sync drain of the sync FET, as well as an inductor coupled between the switch node segment and an output segment of the second patterned conductive carrier.

First claim

1 . A semiconductor package comprising:
a first patterned conductive carrier; a control FET having a control drain attached to a first partially etched segment of said first patterned conductive carrier; a sync FET having a sync source and a sync gate attached to respective second and third partially etched segments of said first patterned conductive carrier; a second patterned conductive carrier having a switch node segment situated over a control source of said control FET and over a sync drain of said sync FET; an inductor coupled between said switch node segment and an output segment of said second patterned conductive carrier.

2 . The semiconductor package of claim 1 , wherein said first, second, and third partially etched segments of said first patterned conductive carrier are substantially half-etched.

3 . The semiconductor package of claim 1 , wherein said switch node segment of said second patterned conductive carrier is partially etched.

4 . The semiconductor package of claim 1 , wherein said control FET, said sync FET, and said inductor form an output stage of a power converter.

5 . The semiconductor package of claim 1 , wherein at least one of said first patterned conductive carrier and said second patterned conductive carrier comprises at least a portion of a lead frame.

6 . The semiconductor package of claim 1 , wherein said second patterned conductive carrier comprises at least a portion of a lead frame.

7 . The semiconductor package of claim 1 , wherein said control FET and said sync FET comprise silicon power FETs.

8 . The semiconductor package of claim 1 , wherein said control FET and said sync FET comprise III-Nitride FETs.

9 . The semiconductor package of claim 1 , wherein said control FET and said sync FET comprise III-Nitride high electron mobility transistors (HEMTs).

10 . The semiconductor package of claim 1 , further comprising a driver integrated circuit for driving at least one of said control FET and said sync FET.

11 . A method for fabricating a semiconductor package, said method comprising:
providing a first patterned conductive carrier; attaching a control drain of a control FET to a first partially etched segment of said first patterned conductive carrier; attaching a sync source and a sync gate of a sync FET to respective second and third partially etched segments of said first patterned conductive carrier; attaching a second patterned conductive carrier having a switch node segment for electrically coupling a control source of said control FET to a sync drain of said sync FET; coupling an inductor between said switch node segment and an output segment of said second patterned conductive carrier.

12 . The method of claim 11 , wherein said first, second, and third partially etched segments of said first patterned conductive carrier are substantially half-etched.

13 . The method of claim 11 , wherein said switch node segment of said second patterned conductive carrier is partially etched.

14 . The method of claim 11 , wherein said control FET, said sync FET, and said inductor form an output stage of a power converter.

15 . The method of claim 11 , wherein at least one of said first patterned conductive carrier and said second patterned conductive carrier comprises at least a portion of a lead frame.

16 . The method of claim 11 , wherein said second patterned conductive carrier comprises at least a portion of a lead frame.

17 . The method of claim 11 , wherein said control FET and said sync FET comprise silicon power FETs.

18 . The method of claim 11 , wherein said control FET and said sync FET comprise III-Nitride FETs.

19 . The method of claim 11 , wherein said control FET and said sync FET comprise III-Nitride high electron mobility transistors (HEMTs).

20 . The method of claim 11 , further comprising attaching a driver integrated circuit for driving at least one of said control FET and said sync FET to a fourth partially etched segment of said first patterned conductive carrier.

Assignees

• Int Rectifier Corp

Inventors

• Cho Eung San
• Clavette Dan

Classifications

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/5525

  comprising copper [Cu] · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/811 Primary

  Multiple chips on leadframes · CPC title