Bidirectional MOS device and method for preparing the same

Patent metadata

Field	Value
Publication number	US-9905682-B2
Application number	US-201615372352-A
Country	US
Kind code	B2
Filing date	Dec 7, 2016
Priority date	Dec 23, 2014
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

A bidirectional Metal-Oxide-Semiconductor (MOS) device, including a P-type substrate, and an active region. The active region includes a drift region, a first MOS structure and a second MOS structure; the first MOS structure includes a first P-type body region, a first P+ contact region, a first N+ source region, a first metal electrode, and a first gate structure; the second MOS structure includes a second P-type body region, a second P+ contact region, a second N+ source region, a second metal electrode, and a second gate structure; and the drift region includes a dielectric slot, a first N-type layer, a second N-type layer, and an N-type region. The active region is disposed on the upper surface of the P-type substrate. The first MOS structure and the second MOS structure are symmetrically disposed on two ends of the upper layer of the drift region.

First claim

The invention claimed is:

1. A bidirectional Metal-Oxide-Semiconductor (MOS) device, the device comprising a cell structure, the cell structure comprising:
a P-type substrate; and
an active region; the active region comprising a drift region, a first MOS structure and a second MOS structure; the first MOS structure comprising a first P-type body region, a first P+ contact region, a first N+ source region, a first metal electrode, and a first gate structure; the second MOS structure comprising a second P-type body region, a second P+ contact region, a second N+ source region, a second metal electrode, and a second gate structure; the drift region comprising a dielectric slot, a first N-type layer, a second N-type layer, and an N-type region;

wherein
the active region is disposed on an upper surface of the P-type substrate; the first MOS structure and the second MOS structure are symmetrically disposed on two ends of an upper layer of the drift region;
the first P+ contact region and the first N+ source region are disposed in the first P-type body region; the first metal electrode and the first gate structure are disposed on an upper surface of the first P-type body region; the first P+ contact region and the first N+ source region are independent, and upper surfaces of the first P+ contact region and the first N+ source region are respectively connected to the first metal electrode; the first gate structure is a planar gate structure, and comprises a first planar gate dielectric and a first gate electrode; the first gate electrode is disposed on an upper surface of the first planar gate dielectric;
the second P+ contact region and the second N+ source region are disposed in the second P-type body region; the second metal electrode and the second gate structure are disposed on an upper surface of the second P-type body region; the second P+ contact region and the second N+ source region are independent, and upper surfaces of the second P+ contact region and the second N+ source region are respectively connected to the second metal electrode; the second gate structure is the planar gate structure, and comprises a second planar gate dielectric and a second gate electrode; the second gate electrode is disposed on an upper surface of the second planar gate dielectric;
the first N-type layer and the second N-type layer are symmetrically disposed on two sides of the dielectric slot; the N-type region is disposed beneath the dielectric slot; a lower surface and a side surface of the first P-type body region are connected to the first N-type layer; a lower surface and a side surface of the second P-type body region are connected to the second N-type layer; the first N-type layer and the second N-type layer each are connected to a side surface on an upper end of the dielectric slot; a lower end of the dielectric slot is embedded in the N-type region; a central line of the dielectric slot is coincident with a central line of the N-type region and a central line of the MOS device; upper surfaces of the N-type region are respectively connected to the first N-type layer and the second N-type layer, and a lower surface of the N-type region is connected to the P-type substrate; a width and a depth of the dielectric slot are both larger than widths and depths of the first N-type layer and the second N-type layer; a depth of an embedded part of the dielectric slot is larger than a width of the dielectric slot, the depths of the first N-type layer and the second N-type layer, and a depth of the N-type region from a bottom surface of the dielectric slot to an upper surface of the P-type substrate;
a first P-type region is disposed between the first N-type layer and the P-type substrate; a second P-type region is disposed between the second N-type layer and the P-type substrate; the first P-type region and the second P-type region are symmetrically disposed on two sides of the N-type region, and are connected to side surfaces of the N-type region;
a first filling slot is disposed on one side of the dielectric slot which is near the first N-type layer; a second filling slot is disposed on another side of the dielectric slot which is near the second N-type layer; the first filling slot and the second filling slot are filled with conductive materials, and are symmetrically disposed; widths and depths of the first filling slot and the second filling slot are less than a width and a depth of the dielectric slot; the depths of the first filling slot and the second filling slot are larger than the depths of the first N-type layer and the second N-type layer; an upper part of the first filling slot is connected to a third metal electrode, and an upper part of the second filling slot is connected to a fourth metal electrode; the third metal electrode is in a short connection to the first metal electrode via a first metal wire on a surface of the MOS device; the fourth metal electrode is in a short connection to the second metal electrode via a second metal wire on the surface of the MOS device.

2. The MOS device of claim 1 , wherein a third P-type region is disposed between a lower part of the dielectric slot and the N-type region.

3. The MOS device of claim 1 , wherein a third P-type region is disposed between the dielectric slot and the N-type region; upper parts of the third P-type region are respectively connected to a lower part of the first N-type region and a lower part of the second N-type region.

4. The MOS device of claim 1 , wherein a third N-type layer is disposed between the P-type substrate and the N-type region, the first P-type region, and the second P-type region.

5. A bidirectional Metal-Oxide-Semiconductor (MOS) device, the device comprising a cell structure, the cell structure comprising:
a P-type substrate;
a dielectric buried layer; and
an active region; the active region comprising a drift region, a first MOS structure and a second MOS structure; the first MOS structure comprising a first P-type body region, a first P+ contact region, a first N+ source region, a first metal electrode, and a first gate structure; the second MOS structure comprising a second P-type body region, a second P+ contact region, a second N+ source region, a second metal electrode, and a second gate structure; the drift region comprises a dielectric slot, a first N-type layer, a second N-type layer, and an N-type region;

wherein
the dielectric buried layer is disposed on an upper surface of the P-type substrate, and the active region is disposed on an upper surface of the dielectric buried layer; the first MOS structure and the second MOS structure are symmetrically disposed on two ends of an upper layer of the drift region;
the first P+ contact region and the first N+ source region are disposed in the first P-type body region; the first metal electrode and the first gate structure are disposed on an upper surface of the first P-type body region; the first P+ contact region and the first N+ source region are independent, and upper surfaces of the first P+ contact region and the first N+ source region are respectively connected to the first metal electrode; the first gate structure is a planar gate structure, and comprises a first planar gate dielectric and a first gate electrode; the first gate electrode is disposed on an upper surface of the first planar gate dielectric;
the second P+ contact region and the second N+ source region are disposed in the second P-type body region; the second metal electrode and the second gate structure are disposed on an upper surface of the second P-type body region; the second P+ contact region and the second N+ source region are independent, and upper surfaces of the second P+ contact region and the second N+ source region are respectively connected to the second metal electrode; the second gate structure is

Assignees

• Univ Electronic Sci & Tech China
• Inst Electronic & Information Engineering Dongguan Uestc

Inventors

• Zhang Jinping
• Li Zehong
• Liu Jingxiu
• Ren Min
• Zhang Bo
• Li Zhaoji

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P14/6306

  of the semiconductor materials · CPC title

• H01L29/66386

  Electricity · mapped topic

• H01L21/3065

  Electricity · mapped topic