Transient voltage suppressor (TVS) with reduced breakdown voltage

Patent metadata

Field	Value
Publication number	US-9911728-B2
Application number	US-201715445640-A
Country	US
Kind code	B2
Filing date	Feb 28, 2017
Priority date	Dec 22, 2015
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

A low capacitance transient voltage suppressor with snapback control and a reduced voltage punch-through breakdown mode includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A set of source regions is formed within a top surface of the second epitaxial layer. Implant regions are formed in the second epitaxial layer, with a first implant region located below the first source region.

First claim

What is claimed is:

1. A method for manufacturing a transient voltage suppressor (TVS) device, comprising:
a) forming a first epitaxial layer of a first conductivity type on top of a semiconductor substrate of the first conductivity type;
b) forming a buried layer of a semiconductor material of the first conductivity type within a top surface of the first epitaxial layer;
c) forming an implant layer of semiconductor material of a second conductivity type within the first epitaxial layer, wherein the implant layer is located below the buried layer and a length of the implant layer extends beyond a length of the buried layer;
d) forming a second epitaxial layer of semiconductor material of the first conductivity type on top of the first epitaxial layer;
e) forming a pair of implant regions of semiconductor material of a second conductivity type within the top surface of the second epitaxial layer;
f) forming a punch-through implant region of semiconductor material of a second conductivity type within the top surface of the second epitaxial layer
g) forming a set of source regions of semiconductor material of a first conductivity type within a top surface of the second epitaxial layer, the set of source regions including a first source region located above the punch-through implant region, a second source region located between the first source region and a first of the implant regions, a third source region located between the first implant region and a second implant region and a fourth source region located such that the second implant region is located between the third and fourth source regions, wherein the first implant region is located between the second source region and the third source region, wherein a vertical PN junction is formed by the first source region, the punch-through implant region and second epitaxial layer, a lateral PN junction being formed by the second source region, second epitaxial layer and first implant region, and a lateral PN junction being formed by the third source region, second epitaxial layer and second implant region.

2. The method of claim 1 , further comprising forming a sink region of a p-type semiconductor material formed within the second epitaxial layer, the sink region being located below the punch through implant region and between the first source region and the second source region.

3. The method of claim 1 , wherein the first conductivity type is N and the second conductivity type is P.

4. The method of claim 1 , further comprising forming a sink region of a n-type semiconductor material within the second epitaxial layer, the sink region being located below the fourth source region.

5. The method of claim 4 , further comprising forming a sink region of a p-type semiconductor material within the second epitaxial layer, the sink region being located adjacent the sink region of the n-type semiconductor material.

6. The method of claim 1 , wherein the first epitaxial layer is made of an n-type semiconductor material.

7. The device of claim 6 , wherein the semiconductor material of the buried layer is a heavily doped n-type semiconductor material having a higher concentration of n-type dopants than the first epitaxial layer.

8. The method of claim 6 , wherein the semiconductor material of the first epitaxial layer is an n-type material having a lower n-type doping concentration than the substrate.

9. A transient voltage suppressor (TVS) device comprising:
a) a semiconductor substrate of a first conductivity type;
b) a first epitaxial layer of a semiconductor material first of the first conductivity type on the substrate;
c) a buried layer of semiconductor material of the first conductivity type located within the first epitaxial layer;
d) an implant layer of a semiconductor material of a second conductivity type located within the first epitaxial layer below the buried layer, the implant layer extending laterally beyond the buried layer, an NPN junction being formed by the buried layer, implant layer, first epitaxial layer and substrate;
e) a second epitaxial layer of semiconductor material of a first conductivity type supported on top of the first epitaxial layer;
f) a pair of implant regions of semiconductor material of a second conductivity type within the top surface of the second epitaxial layer;
g) a punch-through implant region of semiconductor material of a second conductivity type within the top surface of the epitaxial layer; and
h) a set of source regions of semiconductor material of a first conductivity type formed within a top surface of the second epitaxial layer, the set of source regions including a first source region located above the punch-through implant region, a second source region located between the first source region and a first of the implant regions, a third source region located between the first implant region and a second implant region and a fourth source region located such that the second implant region is located between the third and fourth source regions, wherein the first implant region is located between the second source region and the third source region, wherein a vertical PN junction is formed by the first source region, the punch-through implant region and second epitaxial layer, a lateral PN junction being formed by the second source region, second epitaxial layer and first implant region, and a lateral PN junction being formed by the third source region, second epitaxial layer and second implant region.

10. The device of claim 9 , further comprising a sink region of a p-type semiconductor material formed within the second epitaxial layer, the sink region being located below the punch through implant region and between the first source region and the second source region.

11. The device of claim 9 , wherein the substrate is a heavily doped n-type semiconductor substrate.

12. The device of claim 9 , further comprising a sink region of an n-type semiconductor material formed within the second epitaxial layer, the sink region being located below a fourth source region.

13. The device of claim 12 , further comprising a sink region of a p-type semiconductor material formed within the second epitaxial layer, the sink region of the p-type semiconductor material being located adjacent the sink region of the n-type semiconductor material.

14. The device of claim 9 , wherein the first conductivity type is N and the second conductivity type is P.

15. The device of claim 14 , wherein the semiconductor material of the first epitaxial layer is an n-type material having a lower n-type doping concentration than the substrate.

Assignees

• Alpha & Omega Semiconductor

Inventors

• Shi Ning
• Guan Lingpeng
• Bobde Madhur

Classifications

• H01L29/0626

  Electricity · mapped topic

• H01L29/66113

  Electricity · mapped topic

• H01L27/0255

  Electricity · mapped topic

• H01L29/87

  Electricity · mapped topic

• H01L29/7424

  Electricity · mapped topic