Bi-directional punch-through semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9837516-B2
Application number	US-201715587518-A
Country	US
Kind code	B2
Filing date	May 5, 2017
Priority date	Apr 10, 2015
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

In one embodiment, a bi-directional punch-through semiconductor device can include: a first transistor in a first region of a semiconductor substrate of a first conductivity type, where the first transistor includes a semiconductor buried layer of a second conductivity type in the semiconductor substrate, and a first epitaxy region of an epitaxy semiconductor layer above the semiconductor buried layer, the semiconductor buried layer being configured as a base of the first transistor; and a second transistor coupled in parallel with the first transistor, where the second transistor is in a second region of the semiconductor substrate of the first conductivity type, where the second transistor comprises a second epitaxy region of the epitaxy semiconductor layer above the semiconductor substrate, and a first doped region of the second conductivity type in the second epitaxy region, the first doped region being configured as a base of the second transistor.

First claim

What is claimed is:

1. A method of manufacturing a bi-directional punch-through semiconductor device, the method comprising:
a) forming, in a semiconductor substrate of a first conductivity type, a semiconductor buried layer of a second conductivity type;
b) forming an epitaxy semiconductor layer on said semiconductor substrate, wherein said epitaxy semiconductor layer comprises a first epitaxy region and a second epitaxy region of different conductivity types;
c) forming a first doped region of said second conductivity type in said second epitaxy region;
d) forming a second doped region of said first conductivity type in said first epitaxy region; and
e) forming a third doped region of said first conductivity type in said first doped region.

2. The method of claim 1 , wherein said first epitaxy region is of said second conductivity type.

3. The method of claim 1 , wherein said second epitaxy region is one of an intrinsic characteristic or said first conductivity type.

4. The method of claim 1 , further comprising, after forming said epitaxy semiconductor layer, forming an isolation structure in said epitaxy semiconductor layer, wherein said isolation structure extends to said semiconductor substrate from the surface of said epitaxy semiconductor layer to separate said second epitaxy region from said semiconductor buried layer.

5. The method of claim 1 , further comprising:
a) after forming said second doped region and said third doped region, forming a first electrode contacting with said second and third doped regions; and
b) forming a second electrode that contacts with said semiconductor substrate.

6. The method of claim 1 , wherein said first conductivity type is selected from one of N type and P type, and said second conductivity type is selected from the other of N type and P type.

7. The method of claim 1 , wherein said first and second epitaxy regions are respectively auto-doped by said semiconductor buried layer and said semiconductor substrate.

8. The method of claim 1 , wherein a first transistor comprises a second doped region of said first conductivity type in said first epitaxy region, and a second transistor comprises a third doped region of said first conductivity type in said first doped region.

9. The method of claim 8 , further comprising:
a) forming a first PN junction between said semiconductor buried layer and said semiconductor substrate;
b) forming a second PN junction between said first epitaxy region and said second doped region;
c) forming a third PN junction between said first and third doped regions; and
d) forming a fourth PN junction between said first doped region and said second epitaxy region.

10. The method of claim 9 , further comprising forming an isolation structure for defining active regions of said first and second transistors.

11. The method of claim 10 , wherein said isolation structure comprises a first side that adjoins said semiconductor buried layer and said first epitaxy region, and a second side that adjoins said second epitaxy region.

12. The method of claim 11 , wherein said isolation structure is selected from a trench and a doped diffusion region of said first conductivity type.

13. The method of claim 12 , wherein said doped diffusion region extends to said semiconductor substrate from the surface of said epitaxy semiconductor layer.

14. The method of claim 9 , wherein said punch-through occurs instead of avalanche breakdown when said first and third PN junctions withstand a reverse voltage higher than a breakdown voltage.

15. The method of claim 9 , wherein said first PN junction is punched through by regulating the doping concentration of said semiconductor buried layer and said epitaxy semiconductor layer.

16. The method of claim 9 , wherein said third PN junction is punched through by regulating the doping concentration of said first doped region and said epitaxy semiconductor layer.

Assignees

• Silergy Semiconductor Technology Hangzhou Ltd

Inventors

• Yao Fei
• Wang Shijun
• Qin Bo

Classifications

• H01L29/747

  Electricity · mapped topic

• H01L29/66386

  Electricity · mapped topic

• H01L29/7424 Primary

  Electricity · mapped topic

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D18/80

  Bidirectional devices, e.g. triacs · CPC title