Frequency dividing circuit and semiconductor integrated circuit

Patent metadata

Field	Value
Publication number	US-9900014-B2
Application number	US-201615132824-A
Country	US
Kind code	B2
Filing date	Apr 19, 2016
Priority date	Aug 20, 2014
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A plurality of latch circuits driven at rising of a clock signal and a plurality of latch circuits driven at falling of the clock signal are alternately connected, and generation circuit generates a plurality of frequency divided clock signals with different phases based on combinations of levels of outputs of the plurality of latch circuits.

First claim

What is claimed is:

1. A frequency dividing circuit comprising:
a plurality of latch circuits that include a first plurality of latch circuits driven at a rising of a clock signal and a second plurality of latch circuits driven at a falling of the clock signal, the plurality of latch circuits being connected to each other in series connection in a loop in which each of the first plurality of latch circuits driven at the rising of the clock signal is connected to an adjacent one of the second plurality of latch circuits driven at the falling of the clock signal, such that each of the first plurality and the second plurality of latch circuits are alternately connected to one another and in which a data output node of a prior stage latch circuit is connected to a data input node of a subsequent stage latch circuit that is subsequent to the prior stage latch circuit; and
a generation circuit configured to generate each of a plurality of frequency divided clock signals with different phases, based on combinations of levels of outputs of a pair of a first latch circuit driven at the rising of the clock signal and a second latch circuit driven at the falling of the clock signal, the first latch circuit and the second latch circuit being adjacent to each other, among the plurality of latch circuits.

2. The frequency dividing circuit according to claim 1 , wherein the generation circuit is configured to generate each of the plurality of frequency divided clock signals by performing a logical operation of outputs of the adjacent latch circuits among the plurality of latch circuits.

3. The frequency dividing circuit according to claim 1 ,
wherein the latch circuit driven at the rising of the clock signal is an inverter configured to come to be in a continuity state when the clock signal is at a low level and to come to be in a non-continuity state when the clock signal is at a high level, and
wherein the latch circuit driven at the falling of the clock signal is an inverter configured to come to be in a continuity state when the clock signal is at the high level and to come to be in a non-continuity state when the clock signal is at the low level.

4. The frequency dividing circuit according to claim 3 ,
wherein the inverter includes a first P-channel type transistor, a second P-channel type transistor, a first N-channel type transistor, and a second N-channel type transistor that are connected in series in an order thereof between a supply node of a power supply voltage and a supply node of a reference potential,
wherein gate of one transistor of the first P-channel type transistor and the second P-channel type transistor is connected to a data input terminal of the latch circuit,
wherein the clock signal or a logically inverted signal of the clock signal is supplied to gate of another transistor of the first P-channel type transistor and the second P-channel type transistor,
wherein gate of one transistor of the first N-channel type transistor and the second N-channel type transistor is connected to the data input terminal of the latch circuit, and
wherein the clock signal or the logically inverted signal of the clock signal is supplied to gate of another transistor the first N-channel type transistor and the second N-channel type transistor.

5. The frequency dividing circuit according to claim 1 , wherein:
the generation circuit includes a plurality of exclusive logical sum operation circuits configured to generate the plurality of frequency divided clock signals with different phases by performing logical operations of outputs of the adjacent latch circuits among the plurality of latch circuits, and
each of exclusive logical sum operation circuits includes two inverters connected in parallel, the two inverters configured to operate selectively in correspondence with one input of the exclusive logical sum operation circuit and to invert and output another input of the exclusive logical sum operation circuit.

6. The frequency dividing circuit according to claim 1 , wherein the generation circuit configured to generate, as at least one of the plurality of frequency divided clock signals, a frequency divided clock signal whose cycle being an odd-multiple cycle of a cycle of the clock signal or an odd-multiple cycle of (½) cycle of the clock signal, by performing a plurality of stages of logical operations of combinations of levels of the outputs of the plurality of latch circuits.

7. A semiconductor integrated circuit comprising:
a plurality of latch circuits that include a first plurality of latch circuits driven at a rising of a clock signal and a second plurality of latch circuits driven at a falling of the clock signal, the latch circuits being connected to each other in series connection in a loop in which each of the first plurality of latch circuits driven at the rising of the clock signal is connected to an adjacent one of the second plurality of latch circuits driven at the falling of the clock signal, such that each of the first plurality and the second plurality of latch circuits are alternately connected to one another and in which a data output node of a prior stage latch circuit is connected to a data input node of a subsequent stage latch circuit that is subsequent to the prior stage latch circuit;
a generation circuit configured to generate each of a plurality of frequency divided clock signals with different phases, based on combinations of levels of outputs of a pair of a first latch circuit driven at the rising of the clock signal and a second latch circuit driven at the falling of the clock signal, the first latch circuit and the second latch circuit being adjacent to each other, among the plurality of latch circuits; and
a conversion circuit configured to serial-parallel convert and output inputted serial data based on the plurality of frequency divided clock signals.

8. The semiconductor integrated circuit according to claim 7 , wherein the conversion circuit includes a plurality of latch circuits configured to receive different ones of the plurality of frequency divided clock signals, respectively, each of the plurality of latch circuits being configured to latch and output the serial data based on the received frequency divided clock signal.

9. The semiconductor integrated circuit according to claim 8 , wherein a part of a circuit configuration of a transmission path of the frequency divided clock signal to the latch circuit and a part of a circuit configuration of a transmission path of the serial data to the latch circuit are identical.

10. The semiconductor integrated circuit according to claim 7 , further comprising a processing circuit configured to process output data of the conversion circuit by using one or more frequency divided clock signals generated by the generation circuit.

11. A semiconductor integrated circuit comprising:
a plurality of latch circuits that includes a first plurality of latch circuits driven at a rising of a clock signal and a second plurality of latch circuits driven at a falling of the clock signal, the latch circuits being connected to each other in series connection in a loop in which each of the first plurality of latch circuits driven at the rising of the clock signal is connected to an adjacent one of the second plurality of latch circuits driven at the falling of the clock signal, such that each of the first plurality and the second plurality of latch circuits are alternately connected to one another and in which a data output node of a prior stage latch circuit is connected to a data input node of a subsequent stage latch circuit that is subsequent to the prior stage latch circuit;
a generation circuit configured to generate each of a pluralit

Assignees

• Socionext Inc

Inventors

• Tamura Tetsuro

Classifications

• H03K23/54

  Ring counters, i.e. feedback shift register counters (H03K23/52 takes precedence) · CPC title

• H03K21/12

  with parallel read-out · CPC title

• H03K3/356026

  with synchronous operation (H03K3/356034, H03K3/356052 take precedence) · CPC title

• H03K3/0372

  of the primary-secondary type · CPC title

• H03M9/00

  Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) · CPC title