NVFF monotonic counter and method of implementing same

Patent metadata

Field	Value
Publication number	US-10419004-B2
Application number	US-201715493173-A
Country	US
Kind code	B2
Filing date	Apr 21, 2017
Priority date	Apr 21, 2017
Publication date	Sep 17, 2019
Grant date	Sep 17, 2019

Abstract

A monotonic counter includes a plurality of stages respectively corresponding to a plurality of counting bits of the monotonic counter. At least one of the plurality of stages is a non-volatile flip-flop (NVFF) counter that includes a plurality of NVFFs, each NVFF including a pair of non-volatile memory cells.

First claim

What is claimed is:

1. A monotonic counter, comprising:
a plurality of stages respectively corresponding to a plurality of counting bits of the monotonic counter,
wherein at least one of the plurality of stages is a non-volatile flip-flop (NVFF) counter that includes a plurality of NVFFs, each NVFF including a pair of non-volatile memory cells, and a number of the plurality of stages is the same as a number of the plurality of counting bits of the monotonic counter,
wherein the at least one of the plurality of stages includes:
the plurality of NVFFs connected in series and respectively outputting a plurality of bits, an inverted output of a last one of the series-connected NVFFs being connected to a first one of the series-connected NVFFs;
an exclusive-or (XOR) gate receiving the plurality of NVFF bits and outputting a counting bit;
a detector connected to an output of the XOR gate to receive the counting bit output by the XOR gate and outputting a trigger signal in response to determining that the counting bit transitions from logical value “1” to “0”; and
an increment pulse generator outputting an increment pulse to a next and higher-order stage in response to receiving the trigger signal.

2. The monotonic counter of claim 1 , wherein the NVFF counter is a Johnson ring counter.

3. The monotonic counter of claim 1 , wherein the pair of non-volatile memory cells are selected from resistive random access memory cells, conductive bridging random access memory cells, magnetoresistive random access memory cells, ferroelectric random access memory cells, and phase change memory cells.

4. The monotonic counter of claim 1 , wherein the at least one of the plurality of stages corresponds to a least significant bit (LSB) among the plurality of counting bits of the monotonic counter.

5. The monotonic counter of claim 4 , wherein a number of the plurality of NVFFs included in the at least one of the plurality of stages is determined by M divided by P, where M is a maximum number of counts that the monotonic counter is configured to count, and P is a maximum number of program/erase cycles that a NVFF can endure.

6. The monotonic counter of claim 1 , wherein each one of the NVFFs includes:
a flip-flop section including a pair of nodes having a pair of inverse logical data values; and
a non-volatile section including the pair of non-volatile memory cells respectively connected to the pair of nodes.

7. The monotonic counter of claim 6 , wherein the monotonic counter is coupled to a controller, the monotonic counter being configured to:
in response to a write pulse issued by the controller, write the pair of inverse logical data values on the pair of nodes of the flip-flop section into the pair of non-volatile memory cells, respectively, and
in response to a read pulse issued by the controller, read logical data values stored in the pair of non-volatile memory cells and transfer the logical data values read from the pair of non-volatile memory cells to the pair of nodes of the flip-flop section.

8. The monotonic counter of claim 1 , wherein the number of the plurality of stages is m, and the number of the plurality of counting bits is m,
for a counting bit MC[i], where i=0, 1, . . . , m−1, if 2 m-i is greater than P, where P is an estimated number of program/erase cycles in a life of a NVFF, a stage corresponding to counting bit MC[i] includes 2 m-i /P NVFFs.

9. The monotonic counter of claim 1 ,
wherein the plurality of stages are m stages respectively outputting m intermediate bits MC′[(m−1):0], where m is a positive odd number, and
the monotonic counter further includes an output control circuit including at least one multiplexer, the at least one multiplexer being configured to receive an intermediate bit MC′[(m−1)/2] as a multiplexer control, and to select either one of intermediate bits MC′[i] and MC′[m−1−i] to be output as counting bit MC[i] or MC[m−1−i] of the monotonic counter based on the intermediate bit MC′[(m−1)/2], where i is an integer and 0≤i<(m−1)/2.

10. The monotonic counter of claim 9 , further including:
a clock control circuit including at least one multiplexer, the at least one multiplexer being configured to receive the intermediate bit MC′[(m−1)/2] as a multiplexer control, and to selectively provide either one of intermediate bits MC′[j] and MC′[m−1−j] as an input clock of a stage that outputs an intermediate bit MC′[j+1], where j is an integer and 0≤j<(m−1−j).

11. The monotonic counter of claim 1 ,
wherein the plurality of stages are m stages respectively outputting m intermediate bits MC′[(m−1):0], where m is a positive even number, and
the monotonic counter further includes an output control circuit including at least one multiplexer, the at least one multiplexer being configured to receive an intermediate bit MC′[m/2] as a multiplexer control, and to select either one of intermediate bits MC′[i] and MC′[m−1−i] to be output as counting bit MC[i] or MC[m−1−i] of the monotonic counter based on the intermediate bit MC′[m/2], where i is an integer and 0≤i<m/2.

12. The monotonic counter of claim 11 , further including:
a clock control circuit including at least one multiplexer, the at least one multiplexer being configured to receive the intermediate bit MC′[m/2] as a multiplexer control, and to selectively provide either one of intermediate bits MC′[j] and MC′[m−1−j] as an input clock of a stage that outputs an intermediate bit MC′[j+1], where j is an integer and 0≤j<(m−1−j).

13. A method of implementing a monotonic counter, comprising:
providing a plurality of stages respectively outputting a plurality of output bits, wherein at least one of the plurality of stages is a non-volatile flip-flop (NVFF) counter that includes a plurality of NVFFs, each NVFF including a pair of non-volatile memory cells;
providing an output bit of one of the plurality of stages as an input clock of a next and higher-order stage of the plurality of stages;
providing a pulse as an input clock of a first stage of the plurality of stages; and
providing the plurality of output bits as a plurality of counting bits of the monotonic counter,
wherein a number of the plurality of stages is the same as a number of the plurality of counting bits of the monotonic counter, and
wherein the providing a plurality of stages includes providing the at least one of the plurality of stages, which includes:
connecting the plurality of NVFFs in the at least one of the plurality of stages in series, the plurality of NVFFs respectively outputting a plurality of bits; and
providing the plurality of bits to an exclusive-or (XOR) gate, which receives the plurality of bits and outputs an output bit of the at least one of the plurality of stages.

14. The method of claim 13 , wherein the providing an output bit of one of the plurality of stages as an input clock of a next and higher-order stage of the plurality of stages includes:
determining that the output bit of one of the plurality of stages transitions from logical value “1” to “0”; and
outputting an increment pulse to the next and higher-order stage.

15. The method of claim 13 , wherein the providing a plurality of stages includes providing a NVFF, which includes:
providing a flip-flop section including a pair of nodes having a pair of inverse logical data values; and
providing a non-volatile section including the pair of non-volatile memory cells respectively connected to the pair of nodes.

16. The method of claim 15 , further including:
receiving a write pulse from an external controller; and
writing the pair of inverse logical data value

Assignees

• Winbond Electronics Corp
• Windbond Electronics Corp

Inventors

• Lim Seow Fong
• Lin Chi-Shun

Classifications

• H03K23/52 Primary

  using field-effect transistors · CPC title

• H03K3/356

  Bistable circuits · CPC title

• H03K23/542 Primary

  with crossed-couplings, i.e. Johnson counters · CPC title

• G11C14/009

  and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material · CPC title

• G11C13/0009

  RRAM elements whose operation depends upon chemical change · CPC title