Variable clock divider

Patent metadata

Field	Value
Publication number	US-11749324-B2
Application number	US-202217935016-A
Country	US
Kind code	B2
Filing date	Sep 23, 2022
Priority date	Sep 14, 2020
Publication date	Sep 5, 2023
Grant date	Sep 5, 2023

Abstract

Disclosed herein is an apparatus that includes a first group including a plurality of first latch circuits coupled in series and a second group including a plurality of second latch circuits coupled in series. Each of the first latch circuits performs a latch operation in synchronization with a rise trigger signal. Each of the second latch circuits performs a latch operation in synchronization with a fall trigger signal. The rise and fall trigger signals are alternately activated every even clock cycles or every odd clock cycles. In response to a division ratio, first one or more of the first and second latch circuits are bypassed and second one or more of the first and second latch circuits are cyclically coupled.

First claim

The invention claimed is:

1. An apparatus, comprising:
a first group including a plurality of first latch circuits coupled in series; and
a second group including a plurality of second latch circuits coupled in series, wherein
each of the first latch circuits is configured to perform a latch operation in synchronization with a rise trigger signal,
each of the second latch circuits is configured to perform a latch operation in synchronization with a fall trigger signal, the rise and fall trigger signals being alternately activated every even clock cycles or every odd clock cycles, and
in response to a division ratio, first one or more of the first and second latch circuits are bypassed and second one or more of the first and second latch circuits are cyclically coupled.

2. The apparatus of claim 1 , wherein
the rise trigger signal and the fall trigger signal are alternately activated in synchronization with rise edges of a clock signal for every even clock cycles.

3. The apparatus of claim 1 , wherein the rise trigger signal and the fall trigger signal are alternately activated in synchronization with rise edges of a clock signal for every odd clock cycles.

4. The apparatus of claim 1 , wherein at least one of the first latch circuits in the first group is configured to output the rise trigger signal.

5. The apparatus of claim 4 , wherein when the fall trigger signal is activated, the rise trigger signal is generated by passage of a one-shot pulse through the at least one of the first latch circuits in the first group and at least one of the second latch circuits in the second group.

6. The apparatus of claim 1 , wherein
at least one of the second latch circuits in the second group is configured to output the fall trigger signal.

7. The apparatus of claim 6 , wherein when the rise trigger signal is activated, the fall trigger signal is generated by passage of a one-shot pulse through the at least one of the second latch circuits in the second group and at least one of the first latch circuits in the first group.

8. The apparatus of claim 1 , wherein
the division ratio indicates an even number.

9. The apparatus of claim 1 , wherein
the division ratio indicates an odd number.

10. The apparatus of claim 1 , wherein
the division ratio is designated by a division signal, and the division signal is a control parameter in a mode register circuit.

11. The apparatus of claim 1 , wherein the first group comprises a first shift register circuit, and the second group comprises a second shift register circuit.

12. The apparatus of claim 1 , further configured to output a divided clock signal for a test of a memory cell array in response to the rise trigger signal or the fall trigger signal.

13. An apparatus, comprising:
a test circuit configured to generate signals for a test of a memory cell array in synchronization with a divided clock signal; and
a clock divider circuit configured to generate the divided clock signal in response to a division ratio, the clock divider circuit comprising:
a plurality of first latch circuits coupled in series; and
a plurality of second latch circuits coupled in series, wherein
each of the first latch circuits is configured to perform a latch operation in synchronization with one of a rise trigger signal and a fall trigger signal, the rise and fall trigger signals being alternately activated every odd clock cycles or every even clock cycles,
each of the second latch circuits is configured to perform a latch operation in synchronization with another of the rise trigger signal and the fall trigger signal, and
in response to the division ratio, one or more of the first latch circuits and one or more of the second latch circuits are bypassed, and remaining of the first and second latch circuits are cyclically coupled.

14. The apparatus of claim 13 ,
wherein the rise trigger signal and the fall trigger signal are alternately activated in synchronization with rise edges of a clock signal for every even clock cycles or every odd clock cycles.

15. The apparatus of claim 13 ,
further comprising a third latch circuit configured to be set in response to one of the rise and fall trigger signals and cause the divided clock signal to change from a first logic level to a second logic level.

16. The apparatus of claim 15 , wherein the third latch circuit configured to be reset in response to another of the rise and fall trigger signals and cause the divided clock signal to change from the second logic level to the first logic level.

17. The apparatus of claim 13 , wherein the clock divider circuit is a part of the test circuit.

18. A semiconductor device, comprising:
a memory cell array;
an access control circuit configured to access the memory cell array by using an internal address signal and an internal command signal; and
a test circuit configured to supply the internal address signal and the internal command signal to the access control circuit in synchronization with a first clock signal, the test circuit comprising:
an oscillator circuit configured to generate an oscillator signal;
a clock divider circuit configured to generate a divided clock signal by using a plurality of latch circuits coupled cyclically; and
a multiplexer configured to supply the first clock signal as one of the oscillator signal and the divided clock signal based on a clock selection signal, wherein
the plurality of latch circuits include a first group of latch circuits and a second group of latch circuits,
an output signal of one latch circuit of the first group is a rise trigger signal and an output signal of one latch circuit of the second group is a fall trigger signal,
when the fall trigger signal is activated, the rise trigger signal is generated by passage of a one-shot pulse through the one latch circuit of the first group and at least one latch circuit of the second group and, and
when the rise trigger signal is activated, the fall trigger signal is generated by passage of a one-shot pulse through the one latch circuit of the second group and at least one latch circuit of the first group.

19. The semiconductor device of claim 18 , wherein the rise trigger signal and the fall trigger signal are alternately activated in synchronization with rise edges of a second clock signal for every even clock cycles indicated by a division ratio.

20. The semiconductor device of claim 18 , wherein the rise trigger signal and the fall trigger signal are alternately activated in synchronization with rise edges of a second clock signal for every odd clock cycles indicated by a division ratio.

Assignees

• Micron Technology Inc

Inventors

• Uemura Yutaka

Classifications

• G11C7/222 Primary

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C7/106

  Data output latches · CPC title

• G11C7/1036

  using data shift registers · CPC title

• G11C7/1045

  Read-write mode select circuits · CPC title

• G11C7/1087

  Data input latches · CPC title