Divider circuit

Patent metadata

Field	Value
Publication number	US-10425083-B1
Application number	US-201816040842-A
Country	US
Kind code	B1
Filing date	Jul 20, 2018
Priority date	Jul 20, 2018
Publication date	Sep 24, 2019
Grant date	Sep 24, 2019

Abstract

A divider circuit and method for generating one or more digital signals is presented. The circuit has a first output section for generating a first digital signal. There is a first output section with an output node to output the first digital signal, and a plurality of switches with one or more control switches. The plurality of switches selectively couple the output node to a first voltage and/or to selectively couple the output node to a second voltage, thereby generating the first digital signal. The or each control switch is prevents at least one of (i) the output node being coupled to the first and second voltages simultaneously and (ii) the output node being decoupled from both the first and second voltages simultaneously.

First claim

What is claimed is:

1. A divider circuit for generating one or more digital signals, comprising a first output section, the first output section for generating a first digital signal, the first output section comprising:
an output node configured to output the first digital signal; and
a plurality of switches comprising one or more control switches; wherein:
the plurality of switches are configured to selectively couple the output node to a first voltage and/or to selectively couple the output node to a second voltage, thereby generating the first digital signal; and
the, or each, control switch is configured to prevent the output node being coupled to the first and second voltages simultaneously.

2. The divider circuit of claim 1 , wherein:
the plurality of switches comprises one or more clocked switches, a switching operation of the, or each, clocked switch being controlled by a clock signal received by the, or each, clocked switch; and
the switching operation of the, or each, clocked switch contributes to at least one of the selective coupling of the output node to the first voltage and to the selective coupling of the output node to the second voltage.

3. The divider circuit of claim 2 , wherein:
a clock edge is a rising or falling edge of the clock signal;
a falling edge delay is a time delay between a clock edge that switches the first digital signal from the first voltage to the second voltage and a falling edge of the first digital signal;
a rising edge delay is a time delay between a clock edge that switches the first digital signal from the second voltage to the first voltage and a rising edge of the first digital signal; and
the one or more clocked switches are arranged to provide a substantially equal falling edge delay and rising edge delay.

4. The divider circuit of claim 2 , wherein the one or more clocked switches comprise a first and second clocked switch.

5. The divider circuit of claim 1 , wherein:
a switching operation of the, or each, control switch is controlled by a second digital signal received by the, or each, control switch;
the switching operation of the, or each, control switch contributes to at least one of the selective coupling of the output node to the first voltage and to the selective coupling of the output node to the second voltage; and
the switching operation of the, or each, control switch prevents the output node being coupled to the first and second voltage simultaneously.

6. The divider circuit of claim 5 wherein the second digital signal has an approximately 180° phase difference compared with the first digital signal.

7. The divider circuit of claim 5 , comprising a first latch, the first latch comprising the first output section and a second output section, the second output section arranged to generate the second digital signal and to provide the second digital signal to the first output section.

8. The divider circuit of claim 1 , wherein:
the one or more control switches comprise a first control switch;
the first control switch is arranged to prevent the output node from being coupled to both the first and second voltages simultaneously.

9. The divider circuit of claim 1 , wherein the plurality of switches comprises:
an input switch, a switching operation of the input switch being controlled by a third digital signal received by the input switch; and
the switching operation of the first input switch contributes to at least one of the selective coupling of the output node to the first voltage and to the selective coupling of the output node to the second voltage.

10. The divider circuit of claim 9 , wherein the third digital signal has an approximately 90° phase difference compared with the first digital signal.

11. The divider circuit of claim 9 , comprising a first latch and a second latch, the first latch comprising the first output section and the second latch comprising a third output section, the third output section arranged to generate the third digital signal and to provide the third digital signal to the first output section.

12. The divider circuit of claim 8 , wherein:
the plurality of switches comprises one or more clocked switches, a switching operation of the, or each, clocked switch being controlled by a clock signal received by the, or each, clocked switch; and
the switching operation of the, or each, clocked switch contributes to at least one of the selective coupling of the output node to the first voltage and to the selective coupling of the output node to the second voltage.

13. The divider circuit of claim 12 , wherein:
the one or more clocked switches comprises a first clocked switch and a second clocked switch;
the first clocked switch is arranged to contribute to the selective coupling of the output node to the first voltage; and
the second clocked switch is arranged to contribute to the selective coupling of the output node to the second voltage.

14. The divider circuit of claim 13 , wherein the first clocked switch and the first control switch are coupled in parallel.

15. The divider circuit of claim 13 , wherein the second clocked switch and the second control switch are coupled in series.

16. The divider circuit of claim 1 , wherein the switches are transistors.

17. The divider circuit of claim 1 for generating the first, a second, a third and a fourth digital signal, wherein the four digital signals are in quadrature, the divider circuit comprising:
a first latch comprising the first output section and a second output section;
a second latch comprising a third output section and a fourth output section;
the first latch and second latch coupled together; and
the second, third and fourth output sections are arranged to generate the second digital signal, the third digital signal and the fourth digital signal, respectively.

18. The divider of circuit of claim 1 , wherein the, or each, digital signal has a duty cycle of 25%, 50% or 75%.

19. The divider circuit of claim 1 , wherein the, or each, control switch is cross coupled.

20. The divider circuit of claim 1 , wherein the, or each, control switch is configured to prevent the output node being decoupled from both the first and second voltages simultaneously.

21. The divider circuit of claim 20 , wherein:
a switching operation of the, or each, control switch is controlled by a second digital signal received by the, or each, control switch;
the switching operation of the, or each, control switch contributes to at least one of the selective coupling of the output node to the first voltage and to the selective coupling of the output node to the second voltage; and
the switching operation of the, or each, control switch prevents at least one of the output node being coupled to the first and second voltage simultaneously and the output node being decoupled from both the first and second voltages simultaneously.

22. The divider circuit of claim 20 , wherein:
the one or more control switches comprise a first control switch and a second control switch;
the first control switch is arranged to prevent the output node from being decoupled from both the first and second voltages simultaneously; and
the second control switch is arranged to prevent the output node from being coupled to both the first and second voltages simultaneously.

23. A method for generating one or more digital signals using a divider circuit, comprising a first output section, the first output section for generating a first d

Assignees

• Dialog Semiconductor Bv

Inventors

• Maheshwari Vaibhav
• Papamichail Michail

Classifications

• H03K3/356095

  with synchronous operation · CPC title

• H03K23/52

  using field-effect transistors · CPC title

• H03K21/08 Primary

  Output circuits · CPC title

• H03K7/08

  Duration or width modulation {; Duty cycle modulation} · CPC title