FinFET contact structure and method for forming the same

Patent metadata

Field	Value
Publication number	US-9508718-B2
Application number	US-201414585083-A
Country	US
Kind code	B2
Filing date	Dec 29, 2014
Priority date	Dec 29, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A device comprises a substrate comprising a first portion and a second portion separated by an isolation region, a first gate structure over the first portion, a first drain/source region and a second drain/source region in the first portion and on opposite sides of the first gate structure, wherein the first drain/source region and the second drain/source have concave surfaces, a second gate structure over the second portion and a third drain/source region and a fourth drain/source region in the second portion and on opposite sides of the second gate structure, wherein the third drain/source region and the fourth drain/source have the concave surfaces.

First claim

What is claimed is:

1. A method comprising:
epitaxially growing a first semiconductor material to form a first drain/source region and a second drain/source region in a semiconductor substrate;
applying a first etching process to top surfaces of the first drain/source region and the second drain/source region and forming a first recess in the first drain/source region and a second recess in the second drain/source region as a result of the first etching process, wherein the first drain/source region and the second drain/source region have concave surfaces as a result of the first etching process; and
forming a first drain/source contact and a second drain/source contact, wherein:
a bottom portion of the first drain/source contact is in the first recess; and
a bottom portion of the second drain/source contact is in the second recess.

2. The method of claim 1 , further comprising:
forming a first dislocation plane underlying the first drain/source region; and
forming a second dislocation plane underlying the second drain/source region, wherein the first dislocation plane is in parallel with the second dislocation plane.

3. The method of claim 2 , wherein:
prior to the step of epitaxially growing the first semiconductor material, forming a first gate structure over a semiconductor substrate, wherein the first drain/source region and the second drain/source region are on opposite sides of the first gate structure.

4. The method of claim 3 , further comprising:
forming a second gate structure over a semiconductor substrate;
epitaxially growing a second semiconductor material to form a third drain/source region and a fourth drain/source region in the semiconductor substrate, wherein the third drain/source region and the fourth drain/source region are on opposite sides of the second gate structure; and
applying the first etching process to top surfaces of the third drain/source region and the fourth drain/source region and forming recessed top surfaces of the third drain/source region and the fourth drain/source region as a result of the first etching process.

5. The method of claim 4 , wherein:
the first drain/source region, the second drain/source region and the first gate structure form an n-type transistor; and
the third drain/source region, the fourth drain/source region and the second gate structure form a p-type transistor.

6. The method of claim 1 , wherein:
the first recess and the second recess are formed in comprise middle-of-line (MEOL) processes performed after a front-end-of line (FEOL) process and before a back-end-of-line (BEOL) process.

7. The method of claim 1 , wherein:
a depth of the first recess is in a range from about 5 nm to about 25 nm; and
a depth of the second recess is in a range from about 5 nm to about 25 nm.

8. A method comprising:
epitaxially growing a first semiconductor material in a first portion of a substrate to form a first drain/source region and a second drain/source region;
epitaxially growing a second semiconductor material in a second portion of the substrate to form a third drain/source region and a fourth drain/source region, wherein the first portion and the second portion are separated by an isolation region;
applying an etching process to top surfaces of the first drain/source region, the second drain/source region, the third drain/source region and the fourth drain/source region and forming a first recess in the first drain/source region, a second recess in the second drain/source region, a third recess in the third drain/source region and a fourth recess in the fourth drain/source region as a result of the etching process, wherein the first drain/source region, the second drain/source region, the third drain/source region and the fourth drain/source region have concave surfaces as a result of the etching process; and
forming a first drain/source contact, a second drain/source contact, a third drain/source contact and a fourth drain/source contact, wherein:
a bottom portion of the first drain/source contact is in the first recess;
a bottom portion of the second drain/source contact is in the second recess;
a bottom portion of the third drain/source contact is in the third recess; and
a bottom portion of the fourth drain/source contact is in the fourth recess.

9. The method of claim 8 , further comprising:
forming a first gate structure and a second gate structure over the substrate, wherein:
the first drain/source region and the second drain/source region are on opposite sides of the first gate structure; and
the third drain/source region and the fourth drain/source region are on opposite sides of the second gate structure.

10. The method of claim 9 , wherein:
the first drain/source region, the second drain/source region and the first gate structure form an n-type transistor; and
the third drain/source region, the fourth drain/source region and the second gate structure form a p-type transistor.

11. The method of claim 10 , further comprising:
forming a first trench and a second trench in the first portion of the substrate, wherein the first trench and the second trench are on opposite sides of the first gate structure;
applying a pre-amorphous implantation process to the first portion of the substrate;
depositing a first tensile film layer on sidewalls and bottoms of the first trench and the second trench; and
forming a first dislocation plane underlying the first trench and a second dislocation plane underlying the second trench using an anneal process.

12. The method of claim 8 , wherein:
bottoms of the first recess, the second recess, the third recess and the fourth recess are of a concave surface.

13. The method of claim 8 , wherein:
the first semiconductor material is silicon; and
the second semiconductor material is silicon germanium.

14. A method comprising:
epitaxially growing a first semiconductor material in a substrate to form a first drain/source region and a second drain/source region, wherein top surfaces of the first drain/source region and the second drain/source region are level with top surface of the substrate;
epitaxially growing a second semiconductor material in the substrate to form a third drain/source region and a fourth drain/source region, wherein top surfaces of the third drain/source region and the fourth drain/source region are level with top surface of the substrate;
applying an etching process to top surfaces of the first drain/source region, the second drain/source region, the third drain/source region and the fourth drain/source region, wherein as a result of the etching process, the first drain/source region, the second drain/source region, the third drain/source region and the fourth drain/source region have concave surfaces; and
forming a first drain/source contact, a second drain/source contact, a third drain/source contact and a fourth drain/source contact connected to the first drain/source region, the second drain/source region, the third drain/source region and the fourth drain/source region respectively, wherein at least a portion of each drain/source contact is below the top surface of the substrate.

15. The method of claim 14 , wherein:
the first drain/source region and the second drain/source region form an n-type transistor; and
the third drain/source region and the fourth drain/source region form a p-type transistor.

16. The method of claim 14 , further comprising:
forming a first trench and a second trench on opposite sides of a first gate structure;
depositing an oxide layer over the first trench, the second trench, the first gate st

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Ming-Yuan
• Lin Yen-Po
• Lu Yu-Shan
• Hsu Che-Yuan

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title