Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
Package-on-package device
US9105503B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105503-B2 |
| Application number | US-201314047120-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 7, 2013 |
| Priority date | Feb 1, 2013 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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A package-on-package device includes memory chips side-by-side on a package substrate. Accordingly, it is possible to reduce a thickness of a semiconductor package. Further, data and command pads of a logic chip may be located to be adjacent to data and command pads of the memory chips. Accordingly, a routing distance between pads can be contracted and thus signal delivery speed can be improved. This makes it possible to improve an operation speed of the device.
First claim
Opening claim text (preview).
What is claimed is: 1. A package-on-package device, comprising: a first semiconductor package including a first package substrate and a logic chip on the first package substrate; and a second semiconductor package on the first semiconductor package, the second semiconductor package including a second package substrate and first and second memory chips mounted side-by-side on a top surface of the second package substrate, wherein the logic chip includes first and second data logic p…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9105503B2 cover?
- A package-on-package device includes memory chips side-by-side on a package substrate. Accordingly, it is possible to reduce a thickness of a semiconductor package. Further, data and command pads of a logic chip may be located to be adjacent to data and command pads of the memory chips. Accordingly, a routing distance between pads can be contracted and thus signal delivery speed can be improved…
- Who is the assignee on this patent?
- Kim Yonghoon, Kang Hyo-Soon, Choi Inho, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).