Liner and barrier applications for subtractive metal integration

Patent metadata

Field	Value
Publication number	US-9899234-B2
Application number	US-201414320245-A
Country	US
Kind code	B2
Filing date	Jun 30, 2014
Priority date	Jun 30, 2014
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

Methods and techniques for fabricating metal interconnects, lines, or vias by subtractive etching and liner deposition methods are provided. Methods involve depositing a blanket copper layer, removing regions of the blanket copper layer to form a pattern, treating the patterned metal, depositing a copper-dielectric interface material such that the copper-dielectric interface material adheres only to the patterned copper, depositing a dielectric barrier layer on the substrate, and depositing a dielectric bulk layer on the substrate.

First claim

What is claimed is:

1. A method of processing a semiconductor substrate, the method comprising:
performing subtractive etching by plasma-based dry etch on a blanket copper layer on the semiconductor substrate to form a plurality of patterned copper features spaced apart from each other, wherein each of the patterned copper features have a copper surface;
treating the patterned copper features to reduce the copper surfaces;
after reducing the copper surfaces, and prior to depositing a bulk dielectric layer over the substrate, selectively depositing a copper-dielectric interface material on the patterned copper features relative to non-copper material on the semiconductor substrate;
the non-copper material selected from the group consisting of tantalum, tantalum nitride, silicon nitride, carbon-doped silicon nitride, oxygen-doped silicon nitride, oxygen-doped silicon carbide, and combinations thereof; and
depositing the dielectric layer over the patterned copper features to fill said space between the patterned copper features.

2. The method of claim 1 , further comprising exposing the patterned copper features to UV light.

3. The method of claim 1 , further comprising depositing a dielectric barrier layer over the patterned copper features prior to depositing the bulk dielectric layer and anisotropically etching the dielectric barrier layer to remove horizontal surfaces of the dielectric barrier layer deposited on the substrate, wherein the dielectric barrier layer is deposited conformally over the patterned copper features.

4. The method of claim 1 , wherein the patterned copper features are treated for a time between about 1 second and about 300 seconds.

5. The method of claim 1 , further comprising, prior to performing subtractive etching, depositing one or more underlayers on the substrate, wherein the blanket copper layer is deposited on the one or more underlayers.

6. The method of claim 5 , wherein one of the one or more underlayers comprises tantalum and/or tantalum nitride.

7. The method of claim 1 , wherein depositing the blanket copper layer forms grains having a size on average greater than a dimension of the patterned copper features formed by the subtractive etching.

8. The method of claim 1 , wherein the copper-dielectric interface material is cobalt deposited by chemical vapor deposition.

9. The method of claim 1 , wherein the adhesion energy of the copper-dielectric interface material to copper is at least about 5 J/m 2 .

10. The method of claim 1 , wherein the copper-dielectric interface material is deposited to a thickness less than about 30 Å.

11. The method of claim 1 , wherein the patterned copper features have aspect ratios between about 5:1 and about 1:1.

12. The method of claim 1 , wherein performing the subtractive etching to form the patterned copper features having the copper surfaces comprises:
depositing the blanket copper layer over the semiconductor substrate, and
patterning the blanket copper layer to form the patterned copper features having the copper surface by removing regions of the blanket copper layer to form the patterned copper features.

13. The method of claim 1 , further comprising, depositing a dielectric barrier layer.

14. The method of claim 13 , wherein the dielectric barrier layer comprises a high-k material, and wherein k is greater than or equal to 3.

15. The method of claim 13 , wherein the dielectric barrier layer is deposited to a thickness less than about 3 nm.

16. The method of claim 13 , further comprising etching the dielectric layer to form at least one dielectric spacer, wherein the at least one dielectric spacer comprises material selected from the group consisting of aluminum oxide, SiOC, SiNC, and silicon oxide.

17. The method of claim 1 , wherein depositing the bulk dielectric layer leaves air gaps.

Assignees

• Lam Res Corp

Inventors

• Wu Hui Jung
• Knisley Thomas Joseph
• Shankar Nagraj
• Shen Meihua
• Hoang John
• Sharma Prithu

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H01J2237/332

  Coating · CPC title

• C23C16/0245

  by etching with a plasma · CPC title

• C23C16/0272

  Deposition of sub-layers, e.g. to promote the adhesion of the main coating · CPC title

• H01J37/32357

  Generation remote from the workpiece, e.g. down-stream · CPC title