Printed circuit board and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9894764-B2
Application number	US-201615096993-A
Country	US
Kind code	B2
Filing date	Apr 12, 2016
Priority date	Jun 26, 2015
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A printed circuit board and a method of manufacturing a printed circuit board are provided. The printed circuit board includes an insulating layer, a circuit layer embedded in the insulating layer, a solder resist layer disposed on one surface of the insulating layer, the solder resist layer having a cavity of a through-hole shape to expose a part of the circuit layer from the insulating layer, and a metal post embedded in the solder resist layer and exposed to outside via an opening of the solder resist layer, and the metal post includes a first post metal layer, a post barrier layer, and a second post metal layer disposed in that order.

First claim

What is claimed is:

1. A printed circuit board comprising:
an insulating layer;
a circuit layer embedded in the insulating layer;
a solder resist layer disposed on one surface of the insulating layer, the solder resist layer having a cavity of a through-hole shape to expose a part of the circuit layer from the insulating layer; and
a metal post embedded in the solder resist layer and exposed to outside via an opening of the solder resist layer,
wherein the metal post comprises a first post metal layer, a post barrier layer, and a second post metal layer disposed in that order, and
wherein the post barrier layer is formed of a material that is different from that of the first post metal layer and the second post metal layer.

2. The printed circuit board of claim 1 , wherein the post barrier layer comprises a material that has a different reactivity to an etchant reactive to the first post metal layer and second post metal layer.

3. The printed circuit board of claim 1 , wherein the circuit layer has a 2 -layered structure comprising a circuit metal layer and a circuit barrier layer, the circuit barrier layer disposed on the circuit metal layer.

4. The printed circuit board of claim 3 , wherein a portion of the circuit layer that is exposed to the outside through the cavity is formed in a single-layered structure comprising a circuit metal layer.

5. The printed circuit board of claim 4 , wherein a thickness of the circuit layer exposed to outside through the cavity is different from a thickness of the insulating layer, and a thickness of the circuit barrier layer is substantially equal to a difference in the thickness of the circuit layer and the thickness of the insulating layer.

6. The printed circuit board of claim 1 , wherein a first surface of the first post metal layer has a smaller diameter than a second surface of the first post metal layer, and a first surface of the second post metal layer has a smaller diameter than a second surface of the second post metal layer.

7. The printed circuit board of claim 6 , wherein the solder resist layer is disposed on an other side of the insulating layer to cover the circuit layer.

8. A method of manufacturing a printed circuit board, the method comprising:
preparing a carrier board comprising:
a carrier inner layer, and
an adhering layer, a first post metal layer, a post barrier layer, and a second post metal layer disposed on the carrier inner layer in that order; forming a circuit barrier layer on the second post metal layer;
forming a build-up layer comprising an insulating layer and a circuit layer embedded in the insulating layer on the circuit barrier layer;

eliminating the carrier inner layer and the adhering layer;
forming a metal post by patterning the first post metal layer, the post barrier layer and the second post metal layer; and
forming a solder resist layer on the insulating layer to embed the metal post in the solder resist layer and expose the metal post to the outside via an opening in the solder resist layer,
wherein the post barrier layer is formed of a material that is different from that of the first post metal layer and the second post metal layer.

9. The method of claim 8 , wherein the post barrier layer is formed of a material that has a different reactivity to an etchant reactive to the first post metal layer and second post metal layer.

10. The method of claim 8 , wherein the forming of the circuit barrier layer comprises forming the circuit barrier layer from a material that is different from that used for the circuit layer and the second post metal layer.

11. The method of claim 10 , wherein the circuit barrier layer is formed of a material that has a different reactivity to an etchant reactive to the circuit layer and the second post metal layer.

12. The method of claim 8 , wherein the forming of the metal post comprises:
forming an etching resist on the other surface of the first post metal layer to cover the upper part of the region to be included in the metal post;
etching the first post metal layer exposed to the outside with a first etchant;
etching the post barrier layer exposed to the outside by the etching of the first post metal layer with a second etchant;
etching the second post metal layer exposed to the outside by the etching of the post barrier layer with the first etchant; and
eliminating the etching resist,
wherein the first post metal layer and the second post metal layer are not reactive to the second etchant, and the post barrier layer is not reactive to the first etchant.

13. The method of claim 8 , wherein the forming of the solder resist layer comprises forming a cavity with a through-hole shape in the solder resist layer.

14. The method of claim 13 , further comprising eliminating the circuit barrier layer exposed to the outside through the cavity formed in the solder resist after forming the solder resist layer.

15. A method of manufacturing a printed circuit board, the method comprising:
obtaining a carrier board comprising a first post metal layer, a post barrier layer, a second post metal layer and a carrier inner layer;
forming a build-up layer on the carrier board, the build-up layer comprising an insulating layer and a circuit layer embedded in the insulating layer;
removing a portion of the carrier board comprising the carrier inner layer;

forming a metal post by patterning the first post metal layer, the post barrier layer and the second post metal layer; and
forming a solder resist layer on the insulating layer to embed the metal post in the solder resist layer and expose the metal post to the outside via an opening in the solder resist layer,
wherein the post barrier layer is formed of a material that is different from that of the first post metal layer and the second post metal layer.

16. The method of claim 15 , wherein the forming of the metal post comprises etching the first post metal layer using a first etchant, and etching the post barrier layer using a second etchant different from the first etchant.

Assignees

• Samsung Electro Mech

Inventors

• Lee Sung Uk
• Seo Il Jong
• Choi Jae Hoon
• Baek Yong Ho

Classifications

• H05K1/115 Primary

  Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

• H05K3/067

  Etchants · CPC title

• H05K2203/0369

  Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist · CPC title

• H05K3/4697

  having cavities, e.g. for mounting components (H05K3/4691 takes precedence) · CPC title

• H05K3/4647

  by applying an insulating layer around previously made via studs · CPC title