Ultra-low drain-source resistance power MOSFET

Patent metadata

Field	Value
Publication number	US-9887266-B2
Application number	US-6971208-A
Country	US
Kind code	B2
Filing date	Feb 11, 2008
Priority date	Mar 21, 2006
Publication date	Feb 6, 2018
Grant date	Feb 6, 2018

Abstract

Ultra-low drain-source resistance power MOSFET. In accordance with an embodiment of the preset invention, a semiconductor device comprises a plurality of trench power MOSFETs. The plurality of trench power MOSFETs is formed in a second epitaxial layer. The second epitaxial layer is formed adjacent and contiguous to a first epitaxial layer. The first epitaxial layer is formed adjacent and contiguous to a substrate highly doped with red Phosphorus. The novel red Phosphorus doped substrate enables a desirable low drain-source resistance.

First claim

What is claimed is:

1. A semiconductor device comprising:
a trench metal oxide semiconductor field effect transistor (MOSFET) including a substrate doped to a concentration of greater than or equal to about 1.0×10 20 atoms per cubic centimeter of red Phosphorus;
a first epitaxial layer disposed in direct contact with said substrate;
a second epitaxial layer disposed above and in direct contact with said first epitaxial layer,
wherein said second epitaxial layer has an n-type conductance; and
a gate trench of said trench MOSFET wholly within said second epitaxial layer.

2. The semiconductor device of claim 1 comprising a drain contact on the back side of said trench MOSFET.

3. The semiconductor device of claim 1 wherein a resistance of said substrate is less than 1.0 milliohms per centimeter.

4. The semiconductor device of claim 1 wherein said first epitaxial layer is for limiting diffusion of said red Phosphorus from said substrate.

5. The semiconductor device of claim 4 wherein said first epitaxial layer is doped to a concentration of greater than or equal to about 1.0×10 18 atoms per cubic centimeter.

6. The semiconductor device of claim 5 further comprising a second epitaxial layer for formation of trench metal oxide semiconductor field effect transistors disposed adjacent to said first epitaxial layer.

7. The semiconductor device of claim 6 wherein said second epitaxial layer is doped to a concentration of greater than or equal to about 1.0×10 16 atoms per cubic centimeter, and wherein the dopant concentration of said second epitaxial layer is less than the doping concentration of said first epitaxial layer.

8. The semiconductor device of claim 7 wherein said second epitaxial layer comprises doping atoms of the set comprising Arsenic and Phosphorus.

9. The semiconductor device of claim 4 wherein said first epitaxial layer comprises Arsenic as a dopant species.

10. The semiconductor of claim 4 further comprising an N-type implanted layer in contact with said substrate and with said first epitaxial layer.

11. The semiconductor device of claim 10 wherein said N-type implanted layer comprises implanted atoms of the set comprising Arsenic and Antimony.

12. The semiconductor of claim 4 further comprising an N-type implanted layer adjacent to a boundary between said substrate and said first epitaxial layer, wherein said N-type implanted layer is below a trench of said trench MOSFET.

13. A semiconductor device comprising:
a trench metal oxide semiconductor field effect transistor (MOSFET) including:
a substrate doped to a concentration of greater than or equal to about 1.0×10 20 atoms per cubic centimeter of red Phosphorus;
a first epitaxial layer formed directly on said substrate;
a second epitaxial layer formed directly on said first epitaxial layer; and
a trench formed entirely in said second epitaxial layer,
wherein said trench comprises a gate of said trench MOSFET.

14. The semiconductor of claim 13 further comprising an N-type implanted layer adjacent to a boundary between said substrate and said first epitaxial layer, wherein said N-type implanted layer is configured to limit the diffusion of red Phosphorus from said substrate.

15. The semiconductor of claim 14 wherein said N-type implanted layer is within said substrate.

16. The semiconductor of claim 14 wherein said N-type implanted layer is within said first epitaxial layer.

17. The semiconductor of claim 14 wherein said N-type implanted layer crosses a boundary between said substrate and said first epitaxial layer.

Assignees

• Chau The Tu
• Shi Sharon
• Chen Qufei
• Hernandez Martin
• Pattanayak Deva
• Terrill Kyle
• Chen Kuo In
• Vishay Siliconix

Inventors

• Chau The Tu
• Shi Sharon
• Chen Qufei
• Hernandez Martin
• Pattanayak Deva
• Terrill Kyle
• Chen Kuo In

Classifications

• H01L29/0878 Primary

  Electricity · mapped topic

• H01L29/7813

  Electricity · mapped topic

• H01L29/167

  Electricity · mapped topic

• H10D62/834

  further characterised by the dopants · CPC title

• H10D30/668

  having trench gate electrodes, e.g. UMOS transistors · CPC title