High mobility power metal-oxide semiconductor field-effect transistors

Patent metadata

Field	Value
Publication number	US-9437424-B2
Application number	US-12366408-A
Country	US
Kind code	B2
Filing date	May 20, 2008
Priority date	Dec 22, 2005
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

High mobility P-channel power metal oxide semiconductor field effect transistors. In accordance with an embodiment of the present invention, a power MOSFET is fabricated such that the holes flow in an inversion/accumulation channel, which is along the (110) crystalline plane, or equivalents, and the current flow is in the [110] direction, or equivalents, when a negative potential is applied to the gate with respect to the source. The enhanced channel mobility of holes leads to a reduction of the channel portion of the on-state resistance, thereby advantageously reducing total “on”resistance of the device.

First claim

What is claimed is:

1. A method comprising:
utilizing a silicon wafer having a surface orientation in a direction;
etching a trench in a (110) plane of said wafer, wherein said etching comprises etching a plurality of perpendicular trenches bounded by (100) planes;
forming first and second source regions adjacent to and parallel to each long edge of said trench; and
forming a gate structure in said trench between said first and second source regions.

2. The method of claim 1 wherein said plurality of perpendicular trenches form closed cells.

3. A trench MOSFET comprising:
a silicon wafer including a surface orientation in a direction;
a trench formed in said silicon wafer in a (110) plane;
a plurality of perpendicular trenches bounded by (110) planes;
first and second source regions adjacent to and parallel to each long edge of said trench; and
a gate structure in said trench between said first and second source regions.

4. The trench MOSFET of claim 3 wherein said plurality of perpendicular trenches form closed cells.

Assignees

• Pattanayak Deva
• Chen Kuo-In
• Chau The-Tu
• Vishay Siliconix

Inventors

• Pattanayak Deva
• Chen Kuo-In
• Chau The-Tu

Classifications

• H10P14/3466

  Crystal orientation · CPC title

• H10P14/3258

  Crystal orientation · CPC title

• H10P14/2926

  Crystal orientations · CPC title

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title