Narrow semiconductor trench structure

Patent metadata

Field	Value
Publication number	US-9685524-B2
Application number	US-37363006-A
Country	US
Kind code	B2
Filing date	Mar 9, 2006
Priority date	Mar 11, 2005
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

Systems and methods for narrow semiconductor trench structures. In a first method embodiment, a method for forming a narrow trench comprises forming a first layer of insulating material on a substrate and creating a trench through the first layer of insulating material and into the substrate. A second insulating material is formed on the first layer and on exposed portions of the trench and the second insulating material is removed from the first layer of insulating material and the bottom of the trench. The trench is filled with an epitaxial material and the first layer of insulating material is removed. A narrow trench is formed by the removal of remaining portions of the second insulating material.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate having a substrate top surface,
a void within said substrate,
wherein said substrate surrounds said void on the sides and bottom of said void;
a region of epitaxial material formed on said bottom of said void and having a top surface substantially planar with said substrate top surface; and
a trench having said substrate on one side and said epitaxial material on the other side,
wherein said trench is characterized as having a width dimension of less than one hundredth of the critical dimension of the semiconductor process used to manufacture said semiconductor device,
wherein epitaxial material is disposed only on one side of said trench,
wherein said critical dimension is 1.0 micron;
wherein said epitaxial material is of opposite carrier type of the substrate; and
further comprising a vertical channel adjacent to said trench.

2. The semiconductor device of claim 1 wherein said trench is characterized as having a width dimension of less than one thousandth of the critical dimension of the semiconductor process used to manufacture said semiconductor device.

Assignees

• Chau The-Tu
• Le Hoang
• Chen Kuo-In
• Vishay Siliconix

Inventors

• Chau The-Tu
• Le Hoang
• Chen Kuo-In

Classifications

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H10W10/011 Primary

  of isolation regions comprising dielectric materials · CPC title

• H01L29/66181 Primary

  Electricity · mapped topic

• H10D1/047 Primary

  of conductor-insulator-semiconductor capacitors, e.g. trench capacitors · CPC title