Narrow semiconductor trench structure

Patent metadata

Field	Value
Publication number	US-9412833-B2
Application number	US-3080908-A
Country	US
Kind code	B2
Filing date	Feb 13, 2008
Priority date	Mar 11, 2005
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

Systems and methods for narrow semiconductor trench structures. In a first method embodiment, a method for forming a narrow trench comprises forming a first layer of insulating material on a substrate and creating a trench through the first layer of insulating material and into the substrate. A second insulating material is formed on the first layer and on exposed portions of the trench and the second insulating material is removed from the first layer of insulating material and the bottom of the trench. The trench is filled with an epitaxial material and the first layer of insulating material is removed. A narrow trench is formed by the removal of remaining portions of the second insulating material.

First claim

What is claimed is:

1. A semiconductor fabrication method for forming a narrow trench, said method comprising:
forming a first layer of insulating material on a substrate;
creating a trench through the first layer of insulating material and into the substrate;
forming a second insulating material on the first layer and on exposed portions of the trench;
removing the second insulating material from the first layer of insulating material and the bottom of the trench;
filling the trench with an epitaxial material;
removing the first layer of insulating material; and
forming a narrow trench by the removal of remaining portions of the second insulating material.

2. The method of claim 1 wherein said forming a first layer of insulating material comprises growing said first layer of insulating material.

3. The method of claim 1 wherein said forming a second insulating material comprises growing said second insulating material.

4. The method of claim 1 wherein said removing the second insulating material comprises applying a blanket dry etching process.

5. The method of claim 1 wherein said filling comprises growing epitaxial material.

6. The method of claim 1 wherein said removing the first layer of insulating material comprises applying chemical mechanical polishing.

7. The method of claim 1 further comprising annealing the substrate at high temperature in a Hydrogen-ambient atmosphere.

Assignees

• Chau The-Tu
• Le Hoang
• Chen Kuo-In
• Vishay Siliconix

Inventors

• Chau The-Tu
• Le Hoang
• Chen Kuo-In

Classifications

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H10W10/011 Primary

  of isolation regions comprising dielectric materials · CPC title

• H10D1/047 Primary

  of conductor-insulator-semiconductor capacitors, e.g. trench capacitors · CPC title

• H01L29/66181 Primary

  Electricity · mapped topic