Structures to avoid floating RESURF layer in high voltage lateral devices

Patent metadata

Field	Value
Publication number	US-9876071-B2
Application number	US-201514634801-A
Country	US
Kind code	B2
Filing date	Feb 28, 2015
Priority date	Feb 28, 2015
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate comprising p-type semiconductor material;
a lateral extended drain n-channel metal oxide semiconductor (LDNMOS) transistor, comprising:
a body of p-type semiconductor material disposed in the substrate; and
a drain drift region of n-type semiconductor material disposed in the substrate, the drain drift region extending laterally to the body;

a p-type layer of semiconductor material disposed in the substrate over at least a portion of the drain drift region, the p-type layer extending from the drain drift region to a top surface of the substrate, the p-type layer having an outermost edge on a side of the p-type layer nearest the body; and
a lateral shunt of p-type semiconductor material disposed in the substrate, the lateral shunt extending to the top surface of the substrate and extending laterally from the p-type layer to the body, wherein a first portion of the outermost edge of the p-type layer adjacent to the lateral shunt is separated from the body by 1 micron to 2 microns more than a second portion of the outermost edge of the p-type layer.

2. The semiconductor device of claim 1 , further comprising a field oxide layer extending over a complete width of the p-type layer.

3. The semiconductor device of claim 1 , wherein the p-type layer is 1 micron to 5 microns thick, and has an average doping density of 1×10 16 cm −3 to 1×10 17 cm −3 .

4. The semiconductor device of claim 1 , wherein the lateral shunt is 1 micron to 5 microns thick, and has an average doping density of 2×10 16 cm −3 to 2×10 17 cm −3 .

5. The semiconductor device of claim 1 , wherein the lateral shunt is 1 micron to 5 microns wide.

6. The semiconductor device of claim 1 , wherein a resistance of the lateral shunt is 1000 ohms to 10000 ohms.

7. The semiconductor device of claim 1 , comprising a plurality of instances of the lateral shunt.

8. A semiconductor device, comprising:
a substrate comprising p-type semiconductor material;
a lateral extended drain n-channel metal oxide semiconductor (LDNMOS) transistor, comprising:
a body of p-type semiconductor material disposed in the substrate; and
a drain drift region of n-type semiconductor material disposed in the substrate, the drain drift region extending laterally to the body;

a p-type layer of semiconductor material disposed in the substrate over at least a portion of the drain drift region, the p-type layer extending from the drain drift region to a top surface of the substrate and the p-type layer extending partially under a gate electrode of the LDNMOS, wherein the p-type layer has an outermost edge on a side of the p-type layer nearest the body;
a field oxide layer extending over the p-type layer past an edge of the gate electrode;
a lateral shunt of p-type semiconductor material disposed in the substrate, the lateral shunt extending to the top surface of the substrate and extending laterally from the p-type layer to the body, wherein a first portion of the outermost edge of the p-type layer adjacent to the lateral shunt is separated from the body by a greater distance than a second portion of the outermost edge of the p-type layer;
a region of higher dopant concentration in the body between a source node and the drain drift region;
a buried region of n-type semiconductor material in the substrate below the body; and
an n-type sinker extending from the buried region to the top surface of the substrate.

9. The semiconductor device of claim 8 , wherein the p-type layer is 1 micron to 5 microns thick, and has an average doping density of 1×10 16 cm −3 to 1×10 17 cm −3 .

10. The semiconductor device of claim 9 , wherein the lateral shunt is 1 micron to 5 microns thick, has an average doping density of 2×10 16 cm −3 to 2×10 17 cm −3 , and is 1 micron to 5 microns wide.

11. The semiconductor device of claim 10 , comprising a plurality of instances of the lateral shunt.

Assignees

• Texas Instruments Inc

Inventors

• Zhang Yongxi
• Hower Philip L
• Lin John
• Mathur Guru
• Balster Scott G
• Bulucea Constantin
• Lee Zachary K
• Pendharkar Sameer P

Classifications

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10D30/603

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title

• H01L29/063 Primary

  Electricity · mapped topic

• H01L29/1095

  Electricity · mapped topic

• H01L29/0692

  Electricity · mapped topic