MOSFET with asymmetric self-aligned contact

Patent metadata

Field	Value
Publication number	US-9640436-B1
Application number	US-201615254096-A
Country	US
Kind code	B1
Filing date	Sep 1, 2016
Priority date	Nov 17, 2015
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A semiconductor device includes a source and drain on a substrate; a first and second gate on the source, and the second gate and a third gate on the drain; a source contact over the source and between the first and second gates, the source contact including first and second portions, the first portion in contact with the source and extending between the first and second gates, and the second portion contacting the first portion and extending over the first and second gates; and a drain contact formed over the drain and between the second and third gates, the drain contact including first and second portions, the first portion contacting the drain, extending between second and third gates, and recessed with respect to the first portion of the source contact, and the second portion in contact with the first portion and extending between and over the second and third gates.

First claim

What is claimed is:

1. A method of making a semiconductor device, the method comprising:
forming a first gate, a second gate, and a third gate on a substrate, the first gate being in contact with a source, the second gate being in contact with the source and a drain, and the third gate being in contact with the drain, the source and the drain being arranged on the substrate;
forming a portion of a source contact on the source, the portion of the source contact contacting the source and extending between the first gate and the second gate;
forming a portion of a drain contact on the drain, the portion of the drain contact contacting the source and extending between the second gate and the third gate; and
recessing the portion of the drain contact to a level below a surface of the second gate and the third gate.

2. The method of claim 1 , wherein the portion of the source contact is a first portion, and further comprising forming a second portion of the source contact on the first portion of the source contact, the second portion contacting the first portion and extending over the first gate and the second gate.

3. The method of claim 2 , wherein the portion of the drain contact is a first portion, and further comprising forming a second portion of the drain contact on the first portion of the drain contact, the second portion contacting the first portion and extending between and over the second gate and the third gate.

4. The method of claim 3 , further comprising depositing an interlayer dielectric (ILD) on the first gate, the second gate, and the third gate after recessing the first portion of the drain contact, the ILD being disposed between the second gate and the third gate on a recessed first portion of the drain contact.

5. The method of claim 4 , further comprising patterning the second portion of the source contact and the second portion of the drain contact by removing portions of the ILD down to the level of the first portion of the source contact and the second portion of the drain contact.

6. The method of claim 5 , wherein patterning the second portion of the drain contact comprises removing the ILD between the second gate and the third gate down to the level of the first portion of the drain contact.

7. The method of claim 1 , wherein the portion of the drain contact after recessing has a height in a range from about 20 to about 40 nanometers (nm).

8. The method of claim 7 , wherein the portion of the source contact extends to about a surface of a gate cap arranged on the first gate or the second gate.

9. The method of claim 7 , wherein the portion of the source contact has a height in a range from about 40 to about 100 nm.

10. The method of claim 3 , wherein the second portion of the drain contact has a length that is less than a length of the second portion of the source contact.

11. The method of claim 3 , wherein the second portion of the drain contact has a length in a range from about 20 to about 50 nm.

12. The method of claim 11 , wherein the second portion of the source contact has a length in a range from about 50 to about 500 nm.

13. The method of claim 3 , wherein the second portion of the drain contact contacts the first portion of the drain contact.

14. The method of claim 1 , wherein the substrate comprises silicon.

15. The method of claim 1 , wherein the substrate comprises silicon germanium.

16. The method of claim 1 , wherein the source and the drain comprise epitaxial growth.

17. The method of claim 1 , wherein the first gate, the second gate, and the third gate each comprise a gate stack.

18. The method of claim 17 , wherein the gate stack comprises a dielectric material, a workfunction metal, and a metal gate conductor material.

19. The method of claim 18 , wherein the dielectric material is a high-k dielectric material.

20. The method of claim 1 , wherein the first gate, the second gate, and the third gate each comprise a gate cap.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Cheng Kangguo
• Miao Xin
• Xie Ruilong
• Yamashita Tenko

Classifications

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title