MOSFET with asymmetric self-aligned contact

Patent metadata

Field	Value
Publication number	US-9698230-B2
Application number	US-201615283951-A
Country	US
Kind code	B2
Filing date	Oct 3, 2016
Priority date	Nov 17, 2015
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

A semiconductor device includes a source and drain on a substrate; a first and second gate on the source, and the second gate and a third gate on the drain; a source contact over the source and between the first and second gates, the source contact including first and second portions, the first portion in contact with the source and extending between the first and second gates, and the second portion contacting the first portion and extending over the first and second gates; and a drain contact formed over the drain and between the second and third gates, the drain contact including first and second portions, the first portion contacting the drain, extending between second and third gates, and recessed with respect to the first portion of the source contact, and the second portion in contact with the first portion and extending between and over the second and third gates.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a source and a drain formed in a substrate;
a first gate and a second gate disposed on the source, and the second gate and a third gate disposed on the drain;
a source contact formed over the source and between the first gate and the second gate, the source contact comprising a first portion and a second portion, the first portion being in contact with the source and extending between the first gate and second gate, and the second portion contacting the first portion and extending over the first gate and the second gate; and
a drain contact formed over the drain and between the second gate and the third gate, the drain contact comprising a first portion and a second portion, the first portion positioned in contact with the drain, extending between the second gate and the third gate, and recessed with respect to the first portion of the source contact such that the first portion of the source contact has a thickness that is greater than a thickness of the first portion of the drain contact, the second portion positioned in contact with the first portion and extending between and over the second gate and the third gate.

2. The semiconductor device of claim 1 , wherein the first portion of the source contact has a thickness in a range from about 20 to about 40 nm.

3. The semiconductor device of claim 2 , wherein the first portion of the drain contact has a thickness in a range from about 40 to about 100 nm.

4. The semiconductor device of claim 1 , wherein the first portion of the drain contact is recessed to a level below the second gate and the third gate.

5. The semiconductor device of claim 1 , wherein the second portion of the drain contact has a length that is less than the length of the second portion of the source contact.

6. The semiconductor device of claim 1 , wherein the second portion of the drain contact has a length in a range from about 20 to about 50 nm.

7. The semiconductor device of claim 6 , wherein the second portion of the source contact has a length in a range from about 50 to about 500 nm.

8. The semiconductor device of claim 1 , wherein the first portion of the source contact extends to about a surface of a gate cap.

9. The semiconductor device of claim 1 , wherein the substrate comprises silicon.

10. The semiconductor device of claim 1 , wherein the substrate comprises silicon germanium.

11. A semiconductor device, comprising:
a source and a drain formed in a substrate;
a first gate and a second gate disposed on the source, the second gate and a third gate disposed on the drain, and the first gate, the second gate, and the third gate each having a spacer arranged on a sidewall;
a source contact formed over the source and between the first gate and the second gate, the source contact comprising a first portion and a second portion, the first portion being in contact with the source and extending from the spacer of the first gate to the spacer of the second gate, and the second portion contacting the first portion and extending over and contacting the spacer of the first gate and the spacer of the second gate; and
a drain contact formed over the drain and between the second gate and the third gate, the drain contact comprising a first portion and a second portion, the first portion positioned in contact with the drain, extending from the spacer of the second gate to the spacer of the third gate, and recessed with respect to the first portion of the source contact such that the first portion of the source contact has a thickness that is greater than a thickness of the first portion of the drain contact, the second portion positioned in contact with the first portion over a central region of the first portion, extending between the second gate and the third gate from the spacer of the second gate to the spacer of the third gate, and extending over and contacting the spacer of the second gate and the spacer of the third gate.

12. The semiconductor device of claim 11 , wherein the first portion of the source contact has a thickness in a range from about 20 to about 40 nm.

13. The semiconductor device of claim 12 , wherein the first portion of the drain contact has a thickness in a range from about 40 to about 100 nm.

14. The semiconductor device of claim 11 , wherein the first portion of the drain contact is recessed to a level below the second gate and the third gate.

15. The semiconductor device of claim 11 , wherein the second portion of the drain contact has a length that is less than the length of the second portion of the source contact.

16. The semiconductor device of claim 11 , wherein the second portion of the drain contact has a length in a range from about 20 to about 50 nm.

17. The semiconductor device of claim 16 , wherein the second portion of the source contact has a length in a range from about 50 to about 500 nm.

18. The semiconductor device of claim 11 , wherein the first portion of the source contact extends to about a surface of a gate cap.

19. The semiconductor device of claim 11 , wherein the substrate comprises silicon.

20. The semiconductor device of claim 11 , wherein the substrate comprises silicon germanium.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Cheng Kangguo
• Miao Xin
• Xie Ruilong
• Yamashita Tenko

Classifications

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title