Wiring substrate and semiconductor device

Patent metadata

Field	Value
Publication number	US-9875957-B2
Application number	US-201514791670-A
Country	US
Kind code	B2
Filing date	Jul 6, 2015
Priority date	Jul 16, 2014
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

A wiring substrate includes a first wiring structure and a second wiring structure. The first wiring structure includes a first insulating layer, which covers a first wiring layer, and a via wiring. A first through hole of the first insulating layer is filled with the via wiring. The second wiring structure includes a second wiring layer and a second insulating layer. The second wiring layer is formed on an upper surface of the first insulating layer and an upper end surface of the via wiring. The second wiring layer partially includes a roughened surface. The second insulating layer is stacked on the upper surface of the first insulating layer and covers the second wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The roughened surface of the second wiring layer has a smaller surface roughness than the first wiring layer.

First claim

The invention claimed is:

1. A wiring substrate comprising:
a first wiring structure; and
a second wiring structure stacked on the first wiring structure;
wherein the first wiring structure includes
a first wiring layer,
a first insulating layer covering the first wiring layer, wherein the first insulating layer includes a first through hole that extends through the first insulating layer in a thickness-wise direction to expose an upper surface of the first wiring layer, and
a via wiring including an upper end surface exposed from an upper surface of the first insulating layer, wherein the first through hole of the first insulating layer is filled with the via wiring;

the second wiring structure includes
a second wiring layer including a first wiring pattern and a second wiring pattern, wherein the first wiring pattern is formed on the upper surface of the first insulating layer and the upper end surface of the via wiring, and wherein the second wiring pattern is formed on the upper surface of the first insulating layer, and
a second insulating layer stacked on the upper surface of the first insulating layer and covering the second wiring layer;

the second wiring structure has a higher wiring density than the first wiring structure;
the first wiring pattern comprises:
a first metal barrier film formed on the upper surface of the first insulating layer and the upper end surface of the via wiring;
a first metal film formed on the first metal barrier film; and
a first metal layer formed on the first metal film, the first metal layer partially including a roughened surface, and partially including a smooth surface
wherein the roughened surface of the first metal layer has a smaller surface roughness than a surface roughness of the first wiring layer; and

the second wiring pattern comprises:
a second metal barrier film formed on the upper surface of the first insulating layer;
a second metal film formed on the second metal barrier film; and
a second metal layer formed on the second metal film,
wherein the second metal barrier film includes a side surface located at an inner side of a side surface of the second metal layer.

2. The wiring substrate according to claim 1 , wherein
a side surface of the second metal film is a smooth side surface having a smaller surface roughness than the surface roughness of the roughened surface of the first metal layer;
an upper surface and the side surface of the second metal layer are, respectively, a smooth upper surface and a smooth side surface that have a smaller surface roughness than the surface roughness of the roughened surface of the first metal layer; and
the side surface of the second metal barrier film is located at an inner side of the smooth side surface of the second metal film and the smooth side surface of the second metal layer.

3. The wiring substrate according to claim 2 , further comprising a protective film formed along the smooth side surface of the second metal film, the side surface of the second metal barrier film, the smooth upper surface of the second metal layer, and the smooth side surface of the second metal layer to cover the second wiring pattern.

4. The wiring substrate according to claim 2 , wherein the second wiring layer further includes a third wiring pattern, the third wiring pattern including
a third metal barrier film formed on the upper surface of the first insulating layer,
a third metal film formed on the third metal barrier film, and
a third metal layer formed on the third metal film;
a side surface of the third metal film is a roughened side surface, wherein the roughened side surface of the third metal film has a surface roughness that is larger than the surface roughness of the smooth side surface of the second metal film and smaller than the surface roughness of the first wiring layer;
an upper surface and a side surface of the third metal layer are, respectively, a roughened upper surface and a roughened side surface, wherein the roughened upper surface and the roughened side surface of the third metal layer have a surface roughness that is larger than the surface roughness of the smooth upper surface and the smooth side surface of the second metal layer and smaller than the surface roughness of the first wiring layer; and
the third metal barrier film includes a peripheral portion that projects toward an outer side from the roughened side surface of the third metal film and the roughened side surface of the third metal layer.

5. The wiring substrate according to claim 2 , wherein
the first metal film includes a roughened side surface and a smooth side surface, wherein the smooth side surface of the first metal film has a smaller surface roughness than the surface roughness of the roughened surface of the first metal layer; and
the first metal layer includes a roughened upper surface, a roughened side surface, a smooth upper surface, and a smooth side surface, wherein
the smooth upper surface and the smooth side surface of the first metal layer have a smaller surface roughness than the surface roughness of the roughened surface of the first metal layer, and
the roughened upper surface and the roughened side surface of the first metal layer have a surface roughness that is larger than the surface roughness of the smooth upper surface and the smooth side surface of the second metal layer and the surface roughness of the smooth upper surface and the smooth side surface of the first metal layer and smaller than the surface roughness of the first wiring layer.

6. The wiring substrate according to claim 1 , wherein
the second wiring structure includes
a third insulating layer stacked on the upper surface of the first insulating layer to cover the second wiring layer, wherein the third insulating layer includes a second through hole that exposes a part of the second wiring layer,
the second insulating layer stacked on the upper surface of the first insulating layer to cover the third insulating layer and the second wiring layer, wherein the second insulating layer includes a third through hole having a larger planar shape than the second through hole at a location overlapping the second through hole in a plan view, and
a third wiring layer including a via wiring to fill the second through hole and the third through hole, wherein the third wiring layer is electrically connected to the second wiring layer and stacked on the second insulating layer.

7. The wiring substrate according to claim 1 , wherein
the first insulating layer is a non-photosensitive insulative resin layer of which a main component is a thermosetting resin; and
the second insulating layer, which contains a photosensitive resin as a main component, is thinner than the first insulating layer.

8. A semiconductor device comprising:
a wiring substrate; and
a semiconductor chip mounted on the wiring substrate;
wherein the wiring substrate includes
a first wiring structure, and
a second wiring structure stacked on the first wiring structure;
wherein the first wiring structure includes
a first wiring layer,
a first insulating layer covering the first wiring layer, wherein the first insulating layer includes a first through hole that extends through the first insulating layer in a thickness-wise direction to expose an upper surface of the first wiring layer, and
a via wiring including an upper end surface exposed from an upper surface of the first insulating layer, wherein the first through hole of the first insulating layer is filled with the via wiring;

the second wiring structure includes
a second wiring layer including a first wiring pattern and a second wiring pattern, wherein the first wiring pattern is formed on the upper surface of the first insula

Assignees

• Shinko Electric Ind Co

Inventors

• Shimizu Noriyoshi
• Gozu Yusuke
• Furuichi Jun
• Rokugawa Akio
• Ito Takashi

Classifications

• H05K3/383

  by microetching · CPC title

• H05K2203/0392

  Pretreatment of metal, e.g. before finish plating, etching · CPC title

• H05K1/114

  Pad being close to via, but not surrounding the via · CPC title

• H05K3/4644

  by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602) · CPC title

• H05K2201/0195

  Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure · CPC title