On-device metrology

Patent metadata

Field	Value
Publication number	US-9875946-B2
Application number	US-201414252323-A
Country	US
Kind code	B2
Filing date	Apr 14, 2014
Priority date	Apr 19, 2013
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

Methods and systems for performing semiconductor metrology directly on device structures are presented. A measurement model is created based on measured training data collected from at least one device structure. The trained measurement model is used to calculate process parameter values, structure parameter values, or both, directly from measurement data collected from device structures of other wafers. In some examples, measurement data from multiple targets is collected for model building, training, and measurement. In some examples, the use of measurement data associated with multiple targets eliminates, or significantly reduces, the effect of under layers in the measurement result, and enables more accurate measurements. Measurement data collected for model building, training, and measurement may be derived from measurements performed by a combination of multiple, different measurement techniques.

First claim

What is claimed is:

1. A method comprising:
providing illumination light to a plurality of measurement sites on a surface of a semiconductor wafer with known variations of at least one process parameter, structure parameter, or both, wherein at least one of the first plurality of sites includes a device structure;
detecting an amount of light from each of the plurality of measurement sites in response to the illumination light;
generating a measured response associated with each of the plurality of measurement sites based on the detected amounts of light, the measured response associated with each of the plurality of measurement sites comprising a first amount of measurement data;
determining an expected response model of each of the at least one known process parameters, structure parameters, or both, each expected response model defining values of the parameter as a function of location on the surface of the semiconductor wafer;
determining an input-output measurement model based at least in part on the first amount of measurement data; and
training the input-output measurement model based on parameter values determined from the expected response model;
receiving a second amount of measurement data associated with measurements of a location on a surface of the semiconductor wafer or another semiconductor wafer;
extracting one or more features from the second amount of measurement data;
determining proximity to a desired measurement target on the surface of the measured semiconductor wafer based at least in part on a comparison of the one or more features with ideal features associated with the desired measurement target;
adjusting the measurement location based on the proximity to the desired measurement target;
receiving a third amount of measurement data associated with measurements of a second plurality of sites on the surface of the measured semiconductor wafer, wherein at least one of the second plurality of sites includes the device structure;
determining at least one process parameter value, at least one structural parameter value, or both, associated with each of the second plurality of sites based on a fitting of the third amount of measurement data to the trained input-output measurement model; and
storing any of the at least one process parameter value, the at least one structural parameter value, or both, in a memory.

2. The method of claim 1 , wherein the first amount of measurement data is associated with measurements of a first plurality of sites with known variations of any of focus, exposure dosage, overlay, and critical dimension over the surface of the semiconductor wafer.

3. The method of claim 1 , further comprising:
extracting one or more features of the first amount of measurement data by reducing a dimension of the first amount of measurement data, and wherein the determining the input-output measurement model is based at least in part on the one or more features.

4. The method of claim 3 , wherein the reducing the dimension of the first amount of measurement data involves any of a principal components analysis, a non-linear principal components analysis, a selection of individual signals from the first amount of measurement data, and a filtering of the first amount of measurement data.

5. The method of claim 1 , wherein the expected response model is a wafer map model, and wherein the determining the wafer map model involves fitting a two dimensional map function to the known process parameters, structure parameters, or both, associated with the first plurality of sites.

6. The method of claim 1 , wherein the device structure is a dedicated on-device metrology structure.

7. The method of claim 6 , wherein at least one of the first plurality of sites includes an assist structure located in a scribe line of the semiconductor wafer.

8. A system comprising:
an illuminator configured to provide illumination light to a plurality of measurement sites on a surface of a semiconductor wafer with known variations of at least one process parameter, structure parameter, or both, wherein at least one of the first plurality of sites includes a device structure;
a detector configured to detect an amount of light from each of the plurality of measurement sites in response to the illumination light and generate a measured response associated with each of the plurality of measurement sites based on the detected amounts of light, the measured response associated with each of the plurality of measurement sites comprising a first amount of measurement data; and
a computing system configured to:
determine an expected response model of each of the at least one known process parameters, structure parameters, or both, each expected response model defining values of the parameter as a function of location on the surface of the semiconductor wafer;
determine an input-output measurement model based at least in part on the first amount of measurement data; and
train the input-output measurement model based on parameter values determined from the expected response model;
receive a second amount of measurement data associated with measurements of a second plurality of sites on a surface of the semiconductor wafer or another semiconductor wafer;
adjust a measurement location on the measured semiconductor wafer based on a proximity to a desired measurement target at one or more of the second plurality of sites;
determine at least one process parameter value, at least one structural parameter value, or both, associated with each of the second plurality of sites based on a fitting of the second amount of measurement data to the trained input-output measurement model; and
store any of the at least one process parameter value, the at least one structural parameter value, or both, in a memory.

9. The system of claim 8 , wherein the computing system is further configured to:
extract one or more features of the first amount of measurement data by reducing a dimension of the first amount of measurement data, and wherein the determining the input-output measurement model is based at least in part on the one or more features.

10. The system of claim 9 , wherein the reducing the dimension of the first amount of measurement data involves any of a principal components analysis, a non-linear principal components analysis, a selection of individual signals from the first amount of measurement data, and a filtering of the first amount of measurement data.

11. The system of claim 8 , wherein the device structure is a dedicated on-device metrology structure.

12. The system of claim 11 , wherein at least one of the first plurality of sites includes an assist structure located in a scribe line of the semiconductor wafer.

13. The system of claim 8 , wherein the adjusting of the measurement location is based at least in part on one or more features extracted from the second amount of measurement data.

14. A method comprising:
providing illumination light at a measurement location to a measurement site on a surface of a first semiconductor wafer wherein the measurement site includes a device structure;
detecting an amount of light from the measurement site in response to the illumination light;
generating a measured response associated with the measurement site based on the detected amounts of light, the measured response comprising a first amount of measurement data;
extracting one or more features from the first amount of measurement data by a computing system, wherein the extracting of the one or more features from the first amount of measurement data involves a principal component analysis;
determining proximity to a desired measur

Assignees

• Kla Tencor Corp

Inventors

• Shchegrov Andrei V
• Madsen Jonathan M
• Pandev Stilian Ivanov
• Levy Ady
• Kandel Daniel
• Adel Michael E
• Tadmor Ori

Classifications

• H10P74/27

  Structural arrangements therefor · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P74/203 Primary

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H01L2924/00

  Electricity · mapped topic

• H01L22/30

  Electricity · mapped topic