Method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9870950-B2
Application number	US-201615371646-A
Country	US
Kind code	B2
Filing date	Dec 7, 2016
Priority date	Dec 9, 2015
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

A method of manufacturing a semiconductor device according to one or more exemplary embodiments of the present inventive concept includes forming a plurality of dummy gates on a substrate. Each of the dummy gates includes a gate mask disposed on an upper surface of each of the dummy gates. A spacer is disposed on at least two sides of the dummy gates. An insulating interlayer is formed on the gate mask and the spacer. A first polishing including chemical mechanical polishing is performed on portions of the gate mask and the insulating interlayer by using a slurry composite having a first mixing ratio. A second polishing including chemical mechanical polishing is formed on remaining portions of the gate mask and the insulating interlayer to expose upper surfaces of the plurality of dummy gates, by using a slurry composite having a second mixing ratio.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming dummy gate structures on a substrate, wherein each of the dummy gate structures comprises a dummy gate and a gate mask disposed on an upper surface of the dummy gate, and wherein spacers are disposed on at least two sides of each of the dummy gate structures;
forming an insulating interlayer on the gate mask and the spacer;
performing a first polishing including chemical mechanical polishing on portions of the gate mask, the spacers, and the insulating interlayer, wherein a polishing ratio of the gate mask and the spacers to the insulating interlayer is 1:1 to 2:1; and
performing a second polishing including chemical mechanical polishing on remaining portions of the gate mask and the insulating interlayer to expose upper surfaces of each of the dummy gates, wherein a polishing ratio of the insulating interlayer to the dummy gate is 50:1 to 300:1.

2. The method of claim 1 , wherein the first polishing uses a slurry composite having a first mixing ratio and the second polishing uses a slurry composite having a second mixing ratio,
wherein the slurry composite comprises an abrasive and an additive capable of adjusting a polishing selection ratio, wherein the slurry composite is dispersed in a solvent,
wherein the first mixing ratio of the abrasive and the additive is a ratio of 0.95 to 1.05:1.9 to 2.1, and
wherein the second mixing ratio of the abrasive and the additive is a ratio of 0.95 to 1.05:2.85 to 3.15.

3. The method of claim 2 , wherein the abrasive comprises at least one selected from silica, alumina, ceria, zirconia, and titania.

4. The method of claim 2 , wherein the additive comprises a silicon nitride film polishing accelerator, a polysilicon film polishing restrainer, a silicon oxide film polishing regulator, and a planarization regulator,
wherein the silicon nitride film polishing accelerator comprises at least one selected from isoleucine, alanine, glycine, glutamine, threonine, serine, asparagine, tyrosine, cysteine, valine, and leucine,
wherein the polysilicon film polishing restrainer comprises an anionic polymer comprising at least one selected from polyacrylic acid, polyacrylic acid ammonium salt, polymethacrylic acid, polymethacrylic acid ammonium salt, and poly acrylic maleic acid,
wherein the silicon oxide film polishing regulator comprises at least one selected from 1-2-hydroxyethyl-2-pyrrolidone, 4-hydroxyethyl-2-pyrrolidone, maleic anhydride, maleic hydrazide, and malemide, and
wherein the planarization regulator comprises an nonionic polymer comprising at least one selected from polyvinyl alcohol (PVA), ethylene glycol (EG), glycerin, polyethylene glycol (PEG), polypropylene glycol (PPG), and polyvinyl pyrrolidone (PVP).

5. The method of claim 1 , wherein the gate mask comprises a silicon nitride film, each of the spacers comprises a silicon nitride film, each of the dummy gates comprises a polysilicon film, and the insulating interlayer comprises a silicon oxide film.

6. The method of claim 1 , wherein the substrate comprises a first region and a second region,
wherein a thickness of at least one gate mask in the first region is different from a thickness of the gate mask in the second region.

7. The method of claim 1 , wherein the substrate comprises a first region and a second region,
wherein each of the dummy gates has a first width in the first region and a second width in the second region, wherein the first width is different from the second width.

8. The method of claim 1 , wherein performing the first polishing forms upper surfaces of remaining portions of the gate mask and the insulating interlayer to have a substantially same level.

9. The method of claim 1 , wherein the spacers are disposed on at least two sides of the dummy gate and on at least two sides of the gate mask, wherein the at least two sides of the dummy gate and the at least two sides of the gate mask are substantially orthogonal to an upper surface of the substrate.

10. A method of manufacturing a semiconductor device, the method comprising:
providing a substrate comprising a first region and a second region;
forming dummy gate structures on the substrate, wherein each of the dummy gate structures comprises a dummy gate and a gate mask disposed on an upper surface of the dummy gate, wherein spacers are disposed on opposite side surfaces of each of the dummy gate structures, and wherein each of the dummy gates has a first width in the first region and a second width in the second region, wherein the first width is different from the second width;
forming an insulating interlayer on the gate mask and the spacer;
performing a first polishing including chemical mechanical polishing on portions of the gate mask, the spacers, and the insulating interlayer, wherein a polishing ratio of the gate mask and the spacers to the insulating interlayer is 1:1 to 2:1; and
performing a second polishing including chemical mechanical polishing on remaining portions of the gate mask and the insulating interlayer to stop polishing on the upper surfaces of the dummy gates, wherein a polishing ratio of the insulating interlayer to the dummy gate is 50:1 to 300:1.

11. The method of claim 10 , wherein the first polishing uses a slurry composite having a first mixing ratio and the second polishing uses a slurry composite having a second mixing ratio,
wherein materials included in the slurry composites used in the performing of the first polishing and the second polishing are substantially the same as each other,
wherein each of the slurry composites comprises an abrasive and an additive capable of adjusting a polishing selection ratio, wherein the slurry composite is dispersed in a solvent,
wherein the first mixing ratio of the abrasive and the additive is a ratio of 0.95 to 1.05:1.9 to 2.1, and
wherein the second mixing ratio of the abrasive and the additive is a ratio of 0.95 to 1.05:2.85 to 3.15.

12. The method of claim 10 , wherein the gate mask comprises a silicon nitride film, each of the spacers comprises a silicon nitride film, each of the dummy gates comprises a polysilicon film, the insulating interlayer comprises a silicon oxide film, the gate insulating film comprises a high dielectric constant material, and the gate electrode comprises at least one selected from titanium, titanium nitride, tantalum, tantalum nitride, tungsten, copper, aluminum, or a combination thereof.

13. The method of claim 10 , wherein a thickness of at least one gate mask in the first region is different from a thickness of the gate mask in the second region.

14. The method of claim 10 , wherein performing the first polishing forms upper surfaces of remaining portions of the gate mask and the insulating interlayer to have a substantially same level.

15. The method of claim 10 , wherein the spacers are disposed on at least two sides of the dummy gate and on at least two sides of the gate mask, wherein the at least two sides of the dummy gate and the at least two sides of the gate mask are substantially orthogonal to an upper surface of the substrate.

16. The method of claim 10 , further comprising:
forming a trench exposing the substrate by removing the dummy gate;
forming a gate insulating film on a lower surface of the trench; and
forming a gate electrode on the gate insulating film.

17. A method of manufacturing a semiconductor device, the method comprising:
forming dummy gate structures on a substrate, wherein each of the dummy gate structures comprises a dummy gate and a gate mask disp

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hwang Chang-Sun
• Koo Ja-Eung
• Park Jong-Hyung
• Kim Ho-Young
• Bartolome Leian
• Yoon Bo-Un
• Moon Hyoung-Bin

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10D64/013

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H01L21/823481

  Electricity · mapped topic