Metallization layers configured for reduced parasitic capacitance

Patent metadata

Field	Value
Publication number	US-9230913-B1
Application number	US-201414457155-A
Country	US
Kind code	B1
Filing date	Aug 12, 2014
Priority date	Aug 12, 2014
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

Structures and methods to minimize parasitic capacitance in a circuit structure are provided. The structure may include a substrate supporting one or more circuits and one or more metallization layers above the substrate. The metallization layer includes a conductive pattern defined by an array of conductive fill elements, where the conductive fill elements of the array are discrete, electrically isolated elements sized to satisfy, at least in part, a pre-defined minimum area-occupation ratio for a chemical-mechanical polishing of the metallization layer, and to minimize parasitic capacitance within the metallization layer, as well as minimize parasitic capacitance between the metallization layer and the circuit, and if multiple metallization layers are present, between the layers.

First claim

What is claimed is:

1. A structure comprising:
a substrate comprising at least one circuit;
a metallization layer disposed above the substrate, the metallization layer comprising:
a conductive pattern defined, at least in part, by an array of conductive fill elements, the conductive fill elements of the array being discrete, electrically isolated elements;
wherein the conductive fill elements of the array are sized to, at least in part, satisfy a pre-defined minimum area-occupation ratio for a chemical-mechanical polishing of the metallization layer; and,
wherein the conductive pattern is configured to minimize parasitic capacitance within the metallization layer and minimize parasitic capacitance between the metallization layer and the at least one circuit.

2. The structure of claim 1 , wherein the conductive pattern comprises a plurality of rows of the conductive fill elements, the conductive fill elements of at least one row of the plurality of rows being uniformly spaced apart by a pre-defined distance.

3. The structure of claim 2 , wherein the at least one row and an adjoining row of the plurality of rows are also spaced apart by the pre-defined distance.

4. The structure of claim 2 , wherein the plurality of rows comprise at least a first row and a second row, the second row being adjacent to the first row, and conductive fill elements of the first row are aligned in at least one direction with conductive fill elements of the second row to, at least in part, form a plurality of columns of conductive fill elements, wherein the plurality of columns are also spaced apart by the pre-defined distance.

5. The structure of claim 2 , wherein the plurality of rows comprise at least a first row and a second row, the second row being adjacent to the first row, and conductive fill elements of the first row are offset in at least one direction from conductive fill elements of the second row.

6. The structure of claim 5 , wherein conductive elements of the first row and conductive elements of the second row are offset in at least one direction so that a conductive element of the first row aligns with a space intermediate adjacent conductive elements of the second row.

7. The structure of claim 2 , wherein the pre-defined distance is at least 0.18 μm.

8. The structure of claim 1 , wherein the conductive fill elements are homogeneously sized and shaped.

9. The structure of claim 1 , wherein at least one conductive fill element of the conductive fill elements has a regular polygon shape.

10. The structure of claim 9 , wherein the regular polygon shape is a square shape.

11. The structure of claim 10 , wherein a side length of the square shape is less than or equal to 0.24 μm.

12. The structure of claim 9 , wherein the regular polygon shape is an octagon shape.

13. The structure of claim 1 , wherein the conductive fill pattern has an area-occupation ratio of 33% or less.

14. The structure of claim 1 , wherein the metallization layer is a first metallization layer, the conductive pattern is a first conductive pattern and the conductive fill elements comprise first conductive fill elements, the structure further comprising:
a second metallization layer comprising a second conductive pattern defined, at least in part, by an array of second conductive fill elements, the second conductive fill elements being discrete, electrically isolated elements;
wherein the second conductive fill elements of the array are sized to satisfy, at least in part, a pre-defined minimum area-occupation ratio for the chemical-mechanical polishing of the second metallization layer; and,
wherein the second conductive pattern is configured to minimize parasitic capacitance within the second metallization layer, to minimize parasitic capacitance between the second metallization layer and the first metallization layer, and to minimize parasitic capacitance between the second metallization layer and the at least one circuit.

15. The structure of claim 14 , wherein the pre-defined distance is a first pre-defined distance, and wherein the second conductive pattern comprises a plurality of rows of the second conductive fill elements, wherein the second conductive fill elements of at least one row of the plurality of rows are uniformly spaced apart by a second pre-defined distance, and the at least one row and an adjoining row of the plurality of rows are also spaced apart by the second pre-defined distance.

16. The structure of claim 14 , wherein the first conductive pattern and the second conductive pattern are arrayed so that the first conductive fill elements of the first conductive pattern are aligned in at least one direction with the second conductive fill elements of the second conductive pattern.

17. The structure of claim 16 , wherein the first conductive fill elements of the first conductive pattern are aligned in at least two directions with the second conductive fill elements of the second conductive pattern to, at least in part, form a plurality of vertically aligned columns of first conductive fill elements and second conductive fill elements.

18. The structure of claim 14 , wherein the first conductive pattern and the second conductive pattern are arrayed so that the first conductive fill elements of the first conductive pattern are offset in at least one direction from the second conductive fill elements of the second conductive pattern.

19. The structure of claim 14 , wherein the first conductive fill elements and the second conductive fill elements are homogeneously sized and shaped.

20. A method comprising:
providing a substrate comprising at least one circuit;
providing a metallization layer above the substrate;
forming a conductive pattern in the metallization layer, the forming comprising:
arraying conductive fill elements in the metallization layer to define the conductive pattern, the conductive fill elements of the array being discrete, electrically isolated elements, the arraying comprising:
sizing the conductive fill elements of the array to, at least in part, satisfy a pre-defined minimum area-occupation ratio for a chemical-mechanical polishing of the metallization layer; and,
configuring the conductive pattern to minimize parasitic capacitance within the metallization layer and between the metallization layer and the at least one circuit.

Assignees

• Globalfoundries Inc

Inventors

• Senapati Biswanath
• Singh Jagar
• Chandrasekaran Karthik

Classifications

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H01L23/528 Primary

  Electricity · mapped topic

• H01L21/76897

  Electricity · mapped topic

• H01L23/5222

  Electricity · mapped topic