Gate structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9035397-B2
Application number	US-201313923943-A
Country	US
Kind code	B2
Filing date	Jun 21, 2013
Priority date	Oct 30, 2012
Publication date	May 19, 2015
Grant date	May 19, 2015

Abstract

A method for manufacturing a gate structure may include the following steps: providing a stack on a substrate, the first stack including (from top to bottom) a dummy layer, a first TiN layer, a TaN layer, a second TiN layer, a high-k first dielectric layer, and an interfacial layer; etching the stack to result in a remaining stack that includes at least a remaining dummy layer, a first remaining TiN layer, and a remaining TaN layer; providing an etching stop layer on the substrate; providing a second dielectric layer on the etching stop layer; performing planarization according to the remaining dummy layer; removing the remaining dummy layer and a first portion of the first remaining TiN layer using a dry etching process; removing a second portion of the first remaining TiN layer using a wet etching process; and providing a metal gate layer on the remaining TaN layer.

First claim

What is claimed is:

1. A method for manufacturing a gate structure, the method comprising:
providing a first stack on a semiconductor substrate, the first stack including a dummy layer, a first TiN layer disposed between the dummy layer and the semiconductor substrate, a TaN layer disposed between the first TiN layer and the semiconductor substrate, a second TiN layer disposed between the TaN layer and the semiconductor substrate, a first dielectric layer disposed between the second TiN layer and the semiconductor substrate, and an interfacial layer disposed between the first dielectric layer and the semiconductor substrate, wherein a dielectric constant of the first dielectric layer is greater than a dielectric constant of a silicon oxide material;
etching the first stack to result in a remaining stack that includes a remaining dummy layer, a first remaining TiN layer disposed between the remaining dummy layer and the semiconductor substrate, a remaining TaN layer disposed between the first remaining TiN layer and the semiconductor substrate, a second remaining TiN layer disposed between the remaining TaN layer and the semiconductor substrate, a first remaining dielectric layer disposed between the second remaining TiN layer and the semiconductor substrate, and a remaining interfacial layer disposed between the first remaining dielectric layer and the semiconductor substrate;
providing a contact etching stop layer on the remaining stack and the semiconductor substrate, wherein the remaining stack is disposed between the semiconductor substrate and a first portion of the contact etching stop layer;
providing a second dielectric layer on the contact etching stop layer, wherein each of a second portion of the contact etching stop layer and a third portion of the contact etching stop layer is disposed between the semiconductor substrate and the second dielectric layer;
after the providing the second dielectric layer, performing planarization according to the remaining dummy layer;
after the planarization, removing the remaining dummy layer and a first portion of the first remaining TiN layer using a dry etching process;
removing a second portion of the first remaining TiN layer using a wet etching process; and
providing a metal gate layer on the remaining TaN layer with the remaining TaN layer being disposed between the second remaining TiN layer and the metal gate layer.

2. The method of claim 1 , wherein the interfacial layer includes SiO 2 or SiON formed by oxidation.

3. The method of claim 1 , wherein the first dielectric layer includes one or more of hafnium oxide, hafnium oxide silicon, hafnium oxynitride, hafnium oxynitride silicon, hafnium oxynitride tantalum, zirconium oxide, zirconium oxynitride, zirconium oxynitride silicon, zirconium oxide silicon, lanthanum oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, and aluminium oxide, is formed through atomic layer deposition, and has a thickness in a range of 10 Å to 30 Å.

4. The method of claim 1 , wherein a TiN—TaN—TiN layer that includes the second TiN layer, the TaN layer, and the first TiN layer is formed through atomic layer deposition, wherein the first TiN layer has a thickness in a range of 10 Å to 30 Å, wherein the TaN layer has a thickness in a range of 10 Å to 30 Å, and wherein the second TiN layer has a thickness in a range of 10 Å to 30 Å.

5. The method of claim 1 , wherein the dummy layer includes poly-Si and is formed through chemical vapour deposition or furnace tube deposition, and wherein the dummy layer has a thickness in a range of 400 Å to 800 Å.

6. The method of claim 1 , wherein the contact etching stop layer includes SiN or SiNO and is formed through chemical vapour deposition.

7. The method of claim 1 , wherein the second dielectric layer includes SiO 2 and is formed through chemical vapour deposition.

8. The method of claim 1 , wherein the planarization is performed using a chemical-mechanical polishing process.

9. The method of claim 1 , wherein the dry etching process includes plasma etching.

10. The method of claim 1 , wherein the wet etching process includes using at least one of a liquid mixture of hydrogen peroxide (H 2 O 2 ) and ammonia water (NH 3 OH) and a liquid mixture of sulphuric acid (H 2 SO 4 ) and hydrogen peroxide (H 2 O 2 ), wherein the liquid mixture of hydrogen peroxide (H 2 O 2 ) and ammonia water (NH 3 OH) has a temperature in a range of 40° C. to 70° C. and includes ammonia water, hydrogen peroxide, and de-ionized water that have a volume ratio of 1:2:50, and wherein the liquid mixture of sulphuric acid (H 2 SO 4 ) and hydrogen peroxide (H 2 O 2 ) has a temperature in a range of 100° C. to 180° C. and includes sulphuric acid and hydrogen peroxide that have a volume ratio of 4:1.

11. The method of claim 1 , wherein the metal gate layer includes one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, and WSi.

Assignees

• Semiconductor Mfg Int Corp
• Semiconductor Mfg Int Shanghai

Inventors

• Li Aileen
• Ni Jinghua
• Han David

Classifications

• H10D64/01318 Primary

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/685

  being perpendicular to the channel plane · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title