Reduction of solder interconnect stress

Patent metadata

Field	Value
Publication number	US-9865557-B1
Application number	US-201615251325-A
Country	US
Kind code	B1
Filing date	Aug 30, 2016
Priority date	Aug 30, 2016
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring electrical contacts within the electrical contact grid may differ relative thereto.

First claim

What is claimed is:

1. A method to fabricate contacts upon an electronic package structure comprising:
forming a shorting layer upon an electronic package structure;
forming a mask upon the shorting layer;
patterning the mask to form a plurality of first contact trenches, wherein a first diagonal trench is diagonally positioned relative to a first horizontal trench and a first vertical trench and wherein a second diagonal trench is diagonally aligned with the first diagonal trench, a second horizontal trench is horizontally aligned with and rotated relative to the first horizontal trench, and a second vertical trench is vertically aligned with and rotated relative to the first vertical trench;
forming conductive material within the plurality of first contact trenches to form a plurality of first contacts; and
removing the mask and removing the shorting layer external to the plurality of first contacts.

2. The method of claim 1 , wherein the plurality of first contact trenches each comprise a major axis and minor axis and wherein the plurality of first contacts each comprise a major axis and minor axis.

3. The method of claim 2 , wherein the first diagonal trench major axis and minor axis intersection is diagonally aligned with the second diagonal trench major axis and minor axis intersection, wherein the first horizontal trench major axis and minor axis intersection is horizontally aligned with the second horizontal trench major axis and minor axis intersection, and wherein the first vertical trench major axis and minor axis intersection is vertically aligned with the second vertical trench major axis and minor axis intersection.

4. The method of claim 1 , wherein the second horizontal trench is rotated toward the second diagonal trench and wherein the second vertical trench is rotated toward the second diagonal trench.

5. The method of claim 1 , wherein the first vertical trench is horizontally aligned with the first diagonal trench and wherein the first horizontal trench is vertically aligned with the first diagonal trench.

6. The method of claim 5 , wherein the second vertical trench is horizontally aligned with the second diagonal trench and wherein the second horizontal trench is vertically aligned with the second diagonal trench.

7. The method of claim 1 , wherein the plurality of first contacts are located within a power/ground region of the electronic package structure.

8. The method of claim 1 , further comprising:
patterning the mask to form a plurality of second contact trenches each comprising diameter axes'
forming conductive material within the plurality of second contact trenches to form a plurality of second contacts; and
removing the mask and removing the shorting layer external to the plurality of second contacts.

9. The method of claim 8 , wherein the plurality of second contacts are located within an input output region of the electronic package structure.

Assignees

• IBM

Inventors

• Call Anson J
• Khanna Vijayeshwar D
• Russell David J
• Tunga Krishna R

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07254

  changes in dispositions · CPC title

• H10W72/248

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W20/43

  Layouts of interconnections · CPC title