Shaped and oriented solder joints

Patent metadata

Field	Value
Publication number	US-9233835-B2
Application number	US-201113992791-A
Country	US
Kind code	B2
Filing date	Dec 6, 2011
Priority date	Dec 6, 2011
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

The present description relates to the field of fabricating microelectronic assemblies, wherein a microelectronic device may be attached to a microelectronic substrate with a plurality of shaped and oriented solder joints. The shaped and oriented solder joints may be substantially oval, wherein the major axis of the substantially oval solder joints may be substantially oriented toward a neutral point or center of the microelectronic device. Embodiments of the shaped and oriented solder joint may reduce the potential of solder joint failure due to stresses, such as from thermal expansion stresses between the microelectronic device and the microelectronic substrate.

First claim

What is claimed is:

1. An apparatus, comprising:
a microelectronic device;
a microelectronic substrate; and
a plurality of interconnects connecting the microelectronic device and the microelectronic substrate, wherein the plurality of interconnects includes a plurality of substantially oval solder bumps which are substantially radially oriented by a major axis thereof toward a neutral point of the microelectronic device, wherein the plurality of interconnects includes a plurality substantially circular conductive pillars, and wherein the substantially oval solder bumps are disposed on the plurality of substantially circular conductive pillars, wherein the microelectronic substrate includes a plurality of line traces to which the substantially oval solder bumps are attached, and wherein at least a portion of each microelectronic substrate line trace is substantially radially oriented toward the microelectronic device neutral point and wherein the substantially oval solder bumps are attached to the microelectronic substrate line trace portions.

2. The apparatus of claim 1 , wherein the plurality of substantially oval solder bumps are grouped into zones, wherein each of the substantially oval solder bumps with each of the zones are substantially radially oriented by a major axis thereof at a common angle toward a neutral point of the microelectronic device.

3. The apparatus of claim 1 , wherein the plurality of conductive pillars comprises a copper-containing material.

4. The apparatus of claim 1 , wherein the microelectronic device includes a microelectronic die and wherein the plurality of substantially oval solder bumps reside outside a periphery of the microelectronic die.

5. The apparatus of claim 1 , wherein the substantially oval solder bumps comprises a lead/tin solder.

6. The apparatus of claim 1 , wherein the substantially oval solder bumps comprise a lead-free solder.

7. An apparatus, comprising:
a microelectronic device;
a microelectronic substrate; and
a plurality of interconnects connecting the microelectronic device and the microelectronic substrate, wherein the plurality of interconnects includes a plurality of substantially oval solder bumps which are substantially radially oriented by a major axis thereof toward a neutral point of the microelectronic device, wherein the microelectronic substrate includes a plurality of line traces to which the substantially oval solder bumps are attached, and wherein at least a portion of each microelectronic substrate line trace is substantially radially oriented toward the microelectronic device neutral point and wherein the substantially oval solder bumps are attached to the microelectronic substrate line trace portions.

8. The apparatus of claim 7 , wherein the plurality of substantially oval solder bumps are grouped into zones, wherein each of the substantially oval solder bumps with each of the zones are substantially radially oriented by a major axis thereof at a common angle toward a neutral point of the microelectronic device.

9. The apparatus of claim 7 , wherein the plurality of interconnects includes a plurality conductive pillars and wherein the substantially oval solder bumps are disposed on the plurality of conductive pillars.

10. The apparatus of claim 9 , wherein the plurality of conductive pillars comprises a copper-containing material.

11. The apparatus of claim 7 , wherein the microelectronic device includes a microelectronic die and wherein the plurality of substantially oval solder bumps reside outside a periphery of the microelectronic die.

12. The apparatus of claim 7 , wherein the substantially oval solder bumps comprises a lead/tin solder.

13. The apparatus of claim 7 , wherein the substantially oval solder bumps comprise a lead-free solder.

Assignees

• Aleksov Aleksandar
• Ganesan Sanka
• Intel Corp

Inventors

• Aleksov Aleksandar
• Ganesan Sanka

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/01257

  by reflowing · CPC title

• H10W72/01255

  by using masks · CPC title

• H10W72/01223

  in liquid form, e.g. by dispensing droplets or by screen printing · CPC title