Semiconductor device including conductive via with buffer layer at tapered portion of conductive via

Patent metadata

Field	Value
Publication number	US-9859191-B2
Application number	US-201615065903-A
Country	US
Kind code	B2
Filing date	Mar 10, 2016
Priority date	Mar 10, 2015
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A semiconductor device includes a semiconductor substrate, a circuit layer including an interlayer insulating layer on an upper surface of the substrate, and a conductive via penetrating through the interlayer insulating layer and the substrate, and electrically connected to the circuit layer. The device further includes an insulating layer surrounding the conductive via, and located between the conductive via and the substrate and between the conductive via and interlayer insulating layer, and a buffer layer located between the insulating layer and the conductive via, and overlapping at least a portion of the interlayer insulating layer in a depth direction of the conductive via.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate with an upper surface and a lower surface opposite the upper surface;
a circuit layer including an interlayer insulating layer on the upper surface of the substrate;
a through electrode penetrating through the interlayer insulating layer and the substrate, and electrically connected to the circuit layer, wherein the through electrode includes a conductive via, and the conductive via includes:
a tapered portion that penetrates through the interlayer insulating layer and that decreases in width in a depth direction of the conductive via; and
a non-tapered portion penetrating through the substrate that is constant in width in the depth direction of the conductive via;

an insulating layer surrounding the conductive via, and located between the conductive via and the substrate and between the conductive via and the interlayer insulating layer; and
a buffer layer located between at least part of the tapered portion of the conductive via and the insulating layer,
wherein the buffer layer is absent between a lower part of the non-tapered portion of the conductive via and the insulating layer.

2. The semiconductor device of claim 1 , wherein the tapered portion of the conductive via extends from an upper surface of the interlayer insulating layer to a lower surface of the interlayer insulating layer, and the non-tapered portion of the conductive via extends from the upper surface of the substrate to the lower surface of the substrate.

3. The semiconductor device of claim 2 , wherein the buffer layer is further located between an upper part of the non-tapered portion of the conductive via and the insulating layer.

4. A semiconductor device, comprising:
a semiconductor substrate with an upper surface and a lower surface opposite the upper surface;
a circuit layer including an interlayer insulating layer on the upper surface of the substrate;
a through electrode penetrating through the interlayer insulating layer and the substrate, and electrically connected to the circuit layer, wherein the through electrode includes a conductive via, and the conductive via includes a tapered portion that penetrates through the interlayer insulating layer and that decreases in width in a depth direction of the conductive via;
an insulating layer surrounding the conductive via, and located between the conductive via and the substrate and between the conductive via and the interlayer insulating layer; and
a buffer layer located between at least part of the tapered portion of the conductive via and the insulating layer,
wherein the conductive via includes a non-tapered portion penetrating through the substrate that is constant in width in the depth direction of the conductive via,
wherein the tapered portion of the conductive via extends from an upper surface of the interlayer insulating layer to a lower surface of the interlayer insulating layer, and the non-tapered portion of the conductive via extends from the upper surface of the substrate to the lower surface of the substrate, and
wherein the buffer layer is not located between an upper part of the non-tapered portion of the conductive via and the insulating layer.

5. The semiconductor device of claim 4 , wherein a thickness of the buffer layer decreases in the depth direction of the conductive via.

6. The semiconductor device of claim 4 , wherein the buffer layer surrounds the tapered portion of the conductive via.

7. The semiconductor device of claim 4 , wherein a minimum inner diameter of the buffer layer is less than a minimum inner diameter of the insulating layer.

8. The semiconductor device of claim 4 , further comprising:
a barrier layer interposed between the conductive via and the insulating layer, and between the conductive via and the buffer layer.

9. The semiconductor device of claim 4 , wherein a thickness of the insulating layer varies in a depth direction of the conductive via.

10. A semiconductor device of claim 4 , wherein the lower surface of the substrate is inactive.

11. The semiconductor device of claim 4 , wherein the buffer layer is further located between an upper part of the non-tapered portion of the conductive via and the insulating layer.

Assignees

• Lee Ho-Jin
• Park Byung Lyul
• An Jin Ho
• Samsung Electronics Co Ltd

Inventors

• Lee Ho-Jin
• Park Byung Lyul
• An Jin Ho

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/0265

  characterised by the sidewall insulation · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title