Semiconductor manufacturing device and processing method

Patent metadata

Field	Value
Publication number	US-9859146-B2
Application number	US-201214238860-A
Country	US
Kind code	B2
Filing date	Aug 13, 2012
Priority date	Aug 17, 2011
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A semiconductor manufacturing device includes a stage, a plurality of pins, and a driving unit. The stage includes a mounting surface. The mounting surface has a first region for mounting thereon a substrate, and a second region for mounting thereon a focus ring. The second region is provided to surround the first region. A plurality of holes is formed in the stage. The holes extend in a direction that intersects the mounting surface while passing through the boundary between the first region and the second region. The pins are provided in the respective holes. Each of the pins has a first and a second upper end surface. The second upper end surface is provided above the first upper end surface, and is offset towards the first region with respect to the first upper end surface. The driving unit moves the pins up and down in the aforementioned direction.

First claim

What is claimed is:

1. A semiconductor manufacturing device comprising:
a processing chamber defining a processing space;
a stage provided in the processing chamber, the stage having a mounting surface which has a first region for mounting thereon a substrate to be processed and a second region for mounting thereon a focus ring, and having a plurality of holes extending in a direction that intersects the mounting surface, the second region of the mounting surface being disposed to surround the first region of the mounting surface;
a plurality of pins which are respectively provided in the holes, each pin having a first upper end surface configured to lift up the focus ring from the second region of the mounting surface and a second upper end surface configured to lift up the substrate from the first region of the mounting surface, wherein the second upper end surface is offset towards the first region of the mounting surface with respect to the first upper end surface and wherein the second upper end surface is located above the first upper end surface;
a driving unit configured to vertically move the pins in the extending direction of the holes; and
a control unit configured to (i) control, in a first mode of lifting up the substrate, the driving unit to move upward the pins to a first height such that the second upper end surfaces of the pins protrude above the first region of the mounting surface to lift the substrate while the first upper end surfaces of the pins are maintained below the second region of the mounting surface and do not lift the focus ring, and (ii) control, in a second mode of lifting up the focus ring, the driving unit to move upward the pins to a second height greater than the first height such that the first upper end surfaces of the pins protrude above the second region of the mounting surface to lift the focus ring,
wherein the first upper end surfaces of the pins are configured to move in unison with the second upper end surfaces of the pins.

2. The semiconductor manufacturing device of claim 1 ,
wherein each pin includes a first columnar portion and a second columnar portion,
wherein the first columnar portion includes the second upper end surface and the second columnar portion includes the first upper end surface, and
wherein a thickness of the first columnar portion is less than a thickness of the second columnar portion.

3. A semiconductor manufacturing device comprising:
a processing chamber defining a processing space;
a stage provided in the processing chamber, the stage having a mounting surface which has a first region for mounting thereon a substrate to be processed and a second region for mounting thereon a focus ring, and having a plurality of holes extending in a direction perpendicular to the mounting surface, the second region of the mounting surface being disposed to surround the first region of the mounting surface;
a plurality of pins which are respectively provided in the holes, each pin including a first columnar portion and a second columnar portion provided above the first columnar portion, the first columnar portion having a first upper end surface configured to lift up the focus ring from the second region of the mounting surface and the second columnar portion having a second upper end surface configured to lift up the substrate from the first region of the mounting surface, wherein the second upper end surface is offset towards the first region of the mounting surface with respect to the first upper end surface and wherein the second upper end surface is located above the first upper end surface;
a driving unit configured to vertically move the pins in the extending direction of the holes; and
a control unit configured to (i) control, in a first mode of lifting up the substrate, the driving unit to move upward the pins to a first height such that the second upper end surfaces of the pins protrude above the first region of the mounting surface to lift the substrate while the first upper end surfaces of the pins are maintained below the second region of the mounting surface and do not lift the focus ring, and (ii) control, in a second mode of lifting up the focus ring, the driving unit to move upward the pins to a second height greater than the first height such that the first upper end surfaces of the pins protrude above the second region of the mounting surface to lift the focus ring,
wherein the first upper end surfaces of the pins are configured to move in unison with the second upper end surfaces of the pins.

Assignees

• Himori Shinji
• Kobayashi Yoshiyuki
• Kato Takehiro
• Ito Etsuji
• Tokyo Electron Ltd

Inventors

• Himori Shinji
• Kobayashi Yoshiyuki
• Kato Takehiro
• Ito Etsuji

Classifications

• H10P72/0418

  for etching · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P72/7612 Primary

  characterised by lifting arrangements, e.g. lift pins · CPC title

• H01L21/67063

  Electricity · mapped topic