Debugging system and debugging method of multi-core processor

Patent metadata

Field	Value
Publication number	US-9852038-B2
Application number	US-201414563317-A
Country	US
Kind code	B2
Filing date	Dec 8, 2014
Priority date	Sep 26, 2014
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

The invention relates to a debugging system and a debugging method of a multi-core processor. The debugging system includes a debugging host, a target processor, and a mapping and protocol conversion device. The debugging host includes a debugger, and the target processor includes a plurality of cores. The mapping and protocol conversion device is connected between the debugging host and the target processor, identifies a core architecture to which each of the cores belongs, and maps each of the cores respectively to at least one thread of at least one process according to the core architecture to which each of the cores belongs. Afterwards, the debugger executes a debugging procedure on the target processor according to the process and the thread corresponded to each of the cores.

First claim

What is claimed is:

1. A debugging system of a multi-core processor, comprising:
a debugging host comprising a debugger executed by a processor of the debugging host;
a target processor comprising a plurality of cores; and
a mapping and protocol conversion device being connected between the debugging host and the target processor, identifying a core architecture of each of the cores, and mapping each of the cores respectively to at least one thread of at least one process of the debugger according to the core architecture to which each of the cores belongs, wherein the mapping and protocol conversion device comprises:
a control server being connected to the debugger through a network interface, controlling the cores being mapped to the threads of the processes; and
a protocol conversion interface device being connected to the control server through a first transmission interface, and being connected to the target processor through a second transmission interface,
wherein the protocol conversion interface device converts data received from the control server into a signal conforming to a protocol standard of the second transmission interface,
wherein the debugger executes a debugging procedure for the target processor to debug the cores of the target processor synchronously through executing the process and the thread corresponded to each of the cores by the processor.

2. The debugging system as claimed in claim 1 , wherein the core architecture at least comprises a first architecture and a second architecture, the mapping and protocol conversion device maps a first core among the cores belonging to the first architecture to a first process among the processes and maps a second core among the cores belonging to the second architecture to a second process among the processes.

3. The debugging system as claimed in claim 1 , wherein the core architecture comprises a first architecture, the cores at least comprise a first core and a second core, when both the first core and the second core belong to the first architecture, the mapping and protocol conversion device maps the first core and the second core together to a first process among the processes, and the mapping and protocol conversion device maps the first core and the second core respectively to a first thread of the first process and a second thread of the first process.

4. The debugging system as claimed in claim 3 , wherein the first core and the second core are operated in a symmetric multiprocessing state.

5. The debugging system as claimed in claim 1 , wherein the core architecture comprises a first architecture, the cores at least comprise a first core and a second core, when both the first core and the second core belong to the first architecture, the mapping and protocol conversion device maps the first core to a first thread of a first process among the processes, and the mapping and protocol conversion device maps the second core to a second thread of a second process among the processes.

6. The debugging system as claimed in claim 5 , wherein the first core and the second core are operated in an asymmetric multiprocessing state.

7. The debugging system as claimed in claim 1 , wherein the debugging host comprises a graphic user interface module, the graphic user interface module provides a user interface to receive an operating command, the debugger outputs a debugging command corresponding to the operating command to the mapping and protocol conversion device.

8. The debugging system as claimed in claim 1 , wherein, when the debugger executes the debugging procedure on the target processor, the target processor outputs core debugging data associated with a first core among the cores to the mapping and protocol conversion device, the mapping and protocol conversion device packages the core debugging data into a debugging message according to one of the processes and one of the threads corresponded to the first core and transmits the debugging message back to the debugger.

9. A debugging method of a multi-core processor, adapted for a debugging system, the debugging system comprising a debugging host, a target processor and a mapping and protocol conversion device, and the target processor comprising a plurality of cores, wherein the debugging method comprises:
connecting the target processor to the mapping and protocol conversion device;
identifying a core architecture to which each of the cores belongs by the mapping and protocol conversion device, and mapping each of the cores to at least one thread of at least one process of a debugger of the debugging host according to the core architecture of each of the cores, wherein the mapping and protocol conversion device comprises a control server and a protocol conversion interface device, the control server is connected to the debugger through a network interface, and the protocol conversion interface device is connected to the control server through a first transmission interface and is connected to the target processor through a second transmission interface,
wherein the step of mapping each of the cores to the at least one thread of the at least one process of the debugger of the debugging host according to the core architecture of each of the cores comprises:
controlling the cores being mapped to the threads of the processes by the control server; and converting data received from the control server into a signal conforming to a protocol standard of the second transmission interface by the protocol conversion interface device; and
executing a debugging procedure for the target processor by the debugger, executed by a processor of the debugging host, of the debugging host so as to debug the cores of the target processor synchronously through executing the processes and the threads corresponded to each of the cores by the processor.

10. The debugging method as claimed in claim 9 , wherein the core architecture at least comprises a first architecture and a second architecture, the mapping and protocol conversion device maps a first core among the cores belonging to the first architecture to a first process among the processes, and maps a second core among the cores belonging to the second architecture to a second process among the processes.

11. The debugging method as claimed in claim 9 , wherein the core architecture comprises a first architecture, the cores at least comprise a first core and a second core, when both the first core and the second core belong to the first architecture, the mapping and protocol conversion device maps the first core and the second core together to a first process among the processes, and the mapping and protocol conversion device maps the first core and the second core respectively to a first thread of the first process and a second thread of the first process.

12. The debugging method as claimed in claim 11 , wherein the first core and the second core are operated in a symmetric multiprocessing state.

13. The debugging method as claimed in claim 9 , wherein the core architecture comprises a first architecture, the cores at least comprise a first core and a second core, when both the first core and the second core belong to the first architecture, the mapping and protocol conversion device maps the first core to a first thread of a first process among the processes, the mapping and protocol conversion device maps the second core to a second thread of a second process among the processes.

14. The debugging method as claimed in claim 13 , wherein the first core and the second core are operated in an asymmetric multiprocessing state.

15. The debugging method as claimed in claim 9

Assignees

• Ali Corp

Inventors

• Kang Yu-Feng
• Wang Qian-Zhi

Classifications

• G06F11/2242 Primary

  in multi-processor systems, e.g. one processor becoming the primary tester (G06F11/2736 takes precedence) · CPC title

• G06F11/36

  Prevention of errors by analysis, debugging or testing of software · CPC title

• G06F11/362

  Debugging of software · CPC title

• G06F11/26 Primary

  Functional testing · CPC title