System and method for multicore processing

Patent metadata

Field	Value
Publication number	US-9304880-B2
Application number	US-201313843090-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 15, 2013
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A method and apparatus for an asynchronous multicore common debugging system is described. Debug signals from a plurality of processor cores are synchronized to a common timing domain. Processing completed within the plurality of processor cores during a common timing interval is tracked. A single debugging tool chain is utilized to provide debugging results in response to the tracking the processing completed within the plurality of processor cores during the common timing interval.

First claim

What is claimed is:

1. A method comprising:
synchronizing debug signals from a plurality of processor cores to a common timing domain;
transmitting debug messages based on the debug signals via a single debug interface common to all processor cores of the plurality of processor cores to enable tracking of processing completed within the plurality of processor cores during a common timing interval.

2. The method of claim 1 wherein the debug messages comprise interprocessor communications (IPC) debug messages based on IPC between at least two processor cores of the plurality of processor cores.

3. The method of claim 1 further comprising:
time stamping the processing completed within the plurality of processor cores during the common timing interval.

4. The method of claim 3 wherein the time stamping further comprises:
obtaining timing information for the time stamping from a first processor core of the plurality of processor cores.

5. The method of claim 3 wherein the time stamping further comprises:
obtaining timing information for the time stamping from a system interconnect coupled to the plurality of processor cores.

6. The method of claim 1 further comprising:
creating synchronization points across the plurality of processor cores based on interprocessor communication (IPC) selected from a group consisting of locks, mutexes, and semaphores to enable the tracking of processing completed within the plurality of processor cores during the common timing interval.

7. The method of claim 1 wherein the plurality of processor cores include processing cores of at least two different types.

8. The method of claim 1 wherein at least two different cores of the plurality of processor cores are not synchronous.

9. The method of claim 1 further comprising:
performing a step debug of the plurality of processor cores based on synchronization with timing information of a first processor core of the plurality of processor cores.

10. The method of claim 1 further comprising:
performing a step debug of the plurality of processor cores based on synchronization with timing information of a system interconnect coupled to the plurality of processor cores.

11. Apparatus comprising:
a plurality of processor cores;
a debug synchronizer coupled to the plurality of processor cores for synchronizing debugging signals from the plurality of processor cores to a common timing domain; and
a debug interface coupled to the debug synchronizer, wherein the debug interface transmits debug information referencing an order of processing completed by the plurality of processor cores with respect to the common timing domain.

12. The apparatus of claim 11 wherein the debug interface transmits debug information for interprocessor communications (IPC) to correlate the processing completed by the plurality of processor cores within an interval of the common timing domain.

13. The apparatus of claim 11 wherein time stamping is applied to a record of the processing completed by the plurality of processor cores, wherein the time stamping is referenced to the common timing domain.

14. The apparatus of claim 11 wherein time stamping is applied to a record of the processing completed by the plurality of processor cores, wherein the time stamping is referenced to a timing of a first core.

15. The apparatus of claim 11 further comprising:
a single common debugging control interface common to all of the plurality of processor cores.

16. A method comprising:
synchronizing system interconnect signals of a plurality of processor cores to a system interconnect timing domain of a system interconnect coupled to the plurality of processor cores;
synchronizing debug signals of a plurality of processor cores to a common timing domain of a common debug interface.

17. The method of claim 16 further comprising:
transmitting via the common debug interface debug messages pertaining to processing completed by the plurality of processor cores during a common timing interval.

18. The method of claim 17 wherein the processing completed by the plurality of processor cores during the common timing interval comprises:
processing completed by the plurality of processor cores within a clock cycle of the common timing interval.

19. The method of claim 18 wherein the clock cycle is selected from a group consisting of a common timing domain clock cycle of the common timing domain, a processor core clock cycle of one processor core of the plurality of processor cores, and a system interconnect clock cycle of the system interconnect.

20. The method of claim 17 wherein the debug messages comprise interprocessor communications (IPC) debug messages based on IPC between at least two processor cores of the plurality of processor cores.

Assignees

• Olivarez Michael L
• Benzel Stephen J
• Ehrlich Robert N
• Mcgowan Robert A
• Freescale Semiconductor Inc

Inventors

• Olivarez Michael L
• Benzel Stephen J
• Ehrlich Robert N
• Mcgowan Robert A

Classifications

• G06F11/2242 Primary

  in multi-processor systems, e.g. one processor becoming the primary tester (G06F11/2736 takes precedence) · CPC title