Implementing processor functional verification by generating and running constrained random irritator tests for multiple processor system and processor core with multiple threads

Patent metadata

Field	Value
Publication number	US-2016162380-A1
Application number	US-201414562908-A
Country	US
Kind code	A1
Filing date	Dec 8, 2014
Priority date	Dec 8, 2014
Publication date	Jun 9, 2016
Grant date	—

Abstract

A method and system are provided for implementing functional verification including generating and running constrained random irritator tests for a multiple processor system and for a processor core with multiple threads. Separate tests are generated, a main test for one thread, and an irritator test for each other thread in the configuration. The main test and each irritator test are saved and randomly mixed then combined together again, where the main thread is not forced to be generated with any particular irritator.

First claim

1 - 9 . (canceled)

10 . A computer system for implementing functional verification including generating and running constrained random irritator tests for a multiple processor system and for a processor core with multiple threads comprising:
a processor; a test generator apparatus receiving a test definition single thread; said processor using said test generator for generating a main test for one thread, and generating an irritator test for each other thread; said processor using said test generator for saving the generated main test and each irritator test and randomly mixing the generated main test and each irritator test; and said processor using said test generator for combining the saved and mixed main test and each irritator test, wherein the main thread is not forced to be generated with any particular irritator.

11 . The system as recited in claim 10 includes control code stored on a computer readable medium, and wherein said processor uses said control code for generating and running constrained random irritator tests.

12 . The system as recited in claim 10 includes said test generator apparatus receiving a test definition with local testing knowledge, allowing said processor using said test generator for generating standard test definitions in either a main or irritator context without modification of the test definition.

13 . The system as recited in claim 12 includes said test generator apparatus receiving test generation context controls and wherein said test generator apparatus includes an irritator generation mode.

14 . The system as recited in claim 10 wherein said test generator apparatus includes an expected exception handling function.

15 . The system as recited in claim 10 wherein said test generator apparatus includes an unexpected exception handler.

16 . The system as recited in claim 15 wherein said processor using said test generator and said unexpected exception handler for returning control of an irritator program stream to a known location and a known state responsive to an unexpected exception interrupt.

17 . The system as recited in claim 10 includes said test generator apparatus receiving a first test definition single thread and a second test definition single thread, each applied to a definition stitcher for definition stitching and generating multi-threaded test definition.

18 . The system as recited in claim 10 includes said test generator apparatus receiving a test definition with local testing knowledge including local instruction class definition for irritator generation mode.

19 . The system as recited in claim 18 wherein said local testing knowledge includes local loop construct for irritator generation mode.

20 . The system as recited in claim 18 wherein said local testing knowledge includes infinite loop construct testing knowledge.

Assignees

• IBM

Inventors

• Hendrickson Olaf K
• Morimoto Yugi
• Mullen Michael P
• Rimon Michal

Classifications

• G01R31/31813

  Test pattern generators · CPC title

• G06F11/2236

  to test CPU or processors · CPC title

• G06F11/263 Primary

  Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers} · CPC title

• G06F11/261

  by simulating additional hardware, e.g. fault simulation · CPC title

• G06F11/2242

  in multi-processor systems, e.g. one processor becoming the primary tester (G06F11/2736 takes precedence) · CPC title