Efficiency of cycle-reproducible debug processes in a multi-core environment

Patent metadata

Field	Value
Publication number	US-9513985-B1
Application number	US-201615013731-A
Country	US
Kind code	B1
Filing date	Feb 2, 2016
Priority date	Jun 29, 2015
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.

First claim

What is claimed is:

1. A method for improving efficiency of cycle-reproducible debug in a multi-core environment, the method comprising:
executing, by one or more computer processors, an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds, wherein executing includes presetting each of the one or more cores with the one or more different seeds, wherein the one or more different seeds are at least one of: a pseudo random value or a binary value, and evaluating the one or more different seeds for each of the one or more cores concurrently;
determining, by one or more computer processors, a seed from the one or more different seeds that locates a fail-condition;
responsive to determining a seed from the one or more different seeds that locates the fail condition, determining, by one or more computer processors, an upper bound and a lower bound of the fail-condition, wherein determining includes executing the exerciser image with the seed on each of the one or more cores for a range of cycles, wherein each of the one or more cores is set to stop at a different cycle within the range of cycles, searching from an initial cycle at the beginning of a test execution run where the fail-condition does not exist to a subsequent cycle of a test execution run where the fail-condition exists, and determining whether the fail-condition has occurred within the range of cycles executed on each of the one or more cores;
responsive to a determination that the fail-condition has occurred within the range of cycles executed by at least one of the one or more cores, determining, by one or more computer processors, a lowest cycle count in the at least one of the one or more cores where the fail-condition as an upper bound;
responsive to a determination that the fail-condition has not occurred within the range of cycles executed by at least one of the one or more cores, resetting, by one or more computer processors, each of the one or more cores with a higher stopping cycle;
determining, by one or more computer processors, an exact cycle where the fail-condition occurs, wherein determining includes performing a plurality of distributed searches for the fail-condition across each of the one or more cores, wherein performing the plurality of distributed searches includes distributing a number of cycles between the upper bound and the lower bound across each of the one or more cores;
constructing, by one or more computer processors, a multi-cycle trace for the fail-condition, wherein constructing includes performing one test execution per-cycle, including the exact cycle where the fail condition occurred, and extracting data from one or more cycles preceding the exact cycle where the fail-condition occurred, data from the exact cycle where the fail-condition occurred, and data from one or more cycles subsequent to the exact cycle where the fail-condition occurred; and
aggregating, by one or more computer processors, test data collected from a plurality of test executions.

Assignees

• IBM

Inventors

• Klazynski James N
• Nahir Amir

Classifications

• G06F11/2236

  to test CPU or processors · CPC title

• G06F11/0724

  in a multiprocessor or a multi-core unit (multiprocessors per se G06F15/80) · CPC title

• G06F11/079 Primary

  Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title

• G06F11/2242 Primary

  in multi-processor systems, e.g. one processor becoming the primary tester (G06F11/2736 takes precedence) · CPC title

• G06F11/362

  Debugging of software · CPC title