Round for reround mode in a decimal floating point instruction

Patent metadata

Field	Value
Publication number	US-9851946-B2
Application number	US-201715470692-A
Country	US
Kind code	B2
Filing date	Mar 27, 2017
Priority date	Mar 1, 2007
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.

First claim

What is claimed is:

1. A computer implemented method for rounding a Decimal Floating Point number to a lesser precision in a computer processor, the method comprising:
a) first emulating, by a computer processor, execution of a decimal floating point instruction to perform a decimal floating point operation utilizing a round-for-reround mode, the first emulating comprising:
fetching from computer processor storage, by the computer processor, a decimal floating point operand having a first number of bits representing a first decimal number, the first decimal number having a first number of decimal digits of precision;
performing in the round-for-reround mode, by the computer processor, the decimal floating point operation on the decimal floating point operand to produce an intermediate result, the intermediate result consisting of a high order portion and a to-be-discarded low order portion, the high order portion consisting of a second number of bits representing a second decimal number, the second decimal number having a least significant decimal digit, the low order portion having a third number of bits;

based on the to-be-discarded low order portion representing a greater-than-0 decimal value, causing the least significant decimal digit to not have a 0 value by setting the least significant bit of the high order portion to 1, wherein the least significant decimal digit having a 0 decimal value indicates the second decimal number is exact; and
storing in computer processor storage, by the computer processor, the high order portion as a final result of the executed decimal floating point operation; and
b) subsequent to first emulating execution of the decimal floating point instruction, second emulating, by the computer processor, execution of a decimal reround instruction, the decimal reround instruction configured to round a decimal floating point number to a designated decimal rounding precision of a plurality of decimal rounding precisions, the second emulating execution of the decimal reround instruction comprising:
fetching from computer processor storage, by the computer processor, the stored final result of the executed decimal floating point operation, the fetched final result having the second number of bits representing the second number of decimal digits;
determining a decimal reround instruction specified second rounding precision of the plurality of rounding precisions, the second rounding precision having at least 2 fewer decimal digits than the first number of decimal digits;
rounding, by the computer processor, the fetched final result to a rounded result, the rounded result representing a decimal number having the at least 2 fewer decimal digits than the first number of decimal digits; and
storing in computer processor storage, by the processor, the rounded final result as a result of the execution of the decimal reround instruction.

2. The computer implemented method according to claim 1 , wherein a least significant decimal digit having a decimal value greater than 0 does not indicate the second decimal number is exact and does not indicate the to-be-discarded low order portion represents a 0 decimal value.

3. The computer implemented method according to claim 1 , wherein the first emulating, by the computer processor, the execution of the decimal floating point instruction configured to perform a decimal floating point operation utilizing a round-for-reround mode is configured to support execution of a subsequent alternative reround instruction for rounding, by the computer processor, the fetched final result to an alternative rounded result, the alternative rounded result representing a decimal number having 1 fewer decimal digits than the first number of decimal digits, wherein based on the to-be-discarded low order portion representing a greater-than-0 decimal value and the least significant decimal digit having a 5 decimal value, causing the least significant decimal digit to not have a 5, wherein the least significant decimal digit having a 5 decimal value indicates the second decimal number is exact.

4. The computer implemented method according to claim 1 , wherein the first emulating, by a computer processor, the execution of the decimal floating point instruction configured to perform the decimal floating point operation utilizing a round-for-reround mode, further comprises pre-rounding, by the computer processor, the high order portion according to a pre-round mode, wherein the pre-rounding mode comprises any one of round toward 0, round away from 0, round toward +infinity, round toward −infinity, round to nearest with ties to even, round to nearest with ties toward 0 and round to nearest with ties away from 0.

5. The computer implemented method according to claim 1 , wherein operands of the decimal floating point operation consist of encoded forms of decimal coefficients, wherein decimal coefficients of encoded forms consist of any one of a binary integer decimal (BID) encoding and a densely packed decimal (DPD) encoding.

6. The computer implemented method according to claim 1 , wherein the executed decimal floating point operation consists of any one of a Multiply, a fused Multiply-and-Add, a Divide, a Convert to BCD, a Convert from BCD, an Add and a Subtract.

7. A computer system for rounding a Decimal Floating Point number to a lesser precision, the computer system comprising:
a computer processor comprising:
an instruction fetching unit for fetching instructions to be executed;
a floating point arithmetic unit for executing floating point operations for executing fetched floating point instructions; and
an operand storage in communication with said floating point arithmetic unit; and

a memory communicatively coupled to said computer processor, the computer system configured to perform a method comprising:
a) first emulating, by the computer processor, execution of a decimal floating point instruction to perform a decimal floating point operation utilizing a round-for-reround mode, the first emulating comprising:
fetching from computer processor storage, by the computer processor, a decimal floating point operand having a first number of bits representing a first decimal number, the first decimal number having a first number of decimal digits of precision;
performing in the round-for-reround mode, by the computer processor, the decimal floating point operation on the decimal floating point operand to produce an intermediate result, the intermediate result consisting of a high order portion and a to-be-discarded low order portion, the high order portion consisting of a second number of bits representing a second decimal number, the second decimal number having a least significant decimal digit, the low order portion having a third number of bits;

based on the to-be-discarded low order portion representing a greater-than-0 decimal value, causing the least significant decimal digit to not have a 0 value by setting the least significant bit of the high order portion to 1, wherein the least significant decimal digit having a 0 decimal value indicates the second decimal number is exact; and
storing in computer processor storage, by the computer processor, the high order portion as a final result of the executed decimal floating point operation; and
b) subsequent to first emulating execution of the decimal floating point instruction, second emulating, by the computer processor, execution of a decimal reround instruction, the decimal reround instruction configured to round a decimal floating point number to a designated decimal rounding precision of a plurality of decimal rounding precisions, the second emulating execution of the decimal reround instruction comprising:
fetching from computer processor storage, by the computer processor, th

Assignees

• IBM

Inventors

• Cowlishaw Michael F
• Schwarz Eric M
• Smith Sr Ronald M
• Yeh Phil C

Classifications

• G06F17/10

  Complex mathematical operations {(function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544)} · CPC title

• G06F7/49957 Primary

  Implementation of IEEE-754 Standard · CPC title

• G06F9/30014

  with variable precision · CPC title

• G06F7/49963

  Rounding to nearest (G06F7/49957 takes precedence) · CPC title

• G06F7/49984

  Rounding away from zero · CPC title