Fused floating point datapath with correct rounding

Patent metadata

Field	Value
Publication number	US-9348557-B1
Application number	US-201414187075-A
Country	US
Kind code	B1
Filing date	Feb 21, 2014
Priority date	Feb 21, 2014
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

In accordance with some embodiments, a floating point number datapath circuitry, e.g., within an integrated circuit programmable logic device is provided. The datapath circuitry may be used for computing a rounded absolute value of a mantissa of a floating point number. The floating point datapath circuitry may have only a single adder stage for computing a rounded absolute value of a mantissa of the floating point number based on one or more bits of an unrounded mantissa of the floating point number. The unrounded and rounded mantissas may include a sign bit, a sticky bit, a round bit, and/or a least significant bit, and/or other bits. The unrounded mantissa may be in a format that includes negative numbers (e.g., 2's complement) and the rounded mantissa may be in a format that may include a portion of the floating point number represented as a positive number, (e.g., signed magnitude).

First claim

What is claimed is:

1. Floating point datapath circuitry, said datapath circuitry comprising:
solely a single adder stage for computing a rounded absolute value of a mantissa of a floating point number based on at least two bits of an unrounded mantissa of the floating point number.

2. The floating point datapath circuitry of claim 1 wherein the at least two bits includes a sign bit.

3. The floating point datapath circuitry of claim 1 wherein the at least two bits includes a sticky bit.

4. The floating point datapath circuitry of claim 1 wherein the at least two bits includes a round bit.

5. The floating point datapath circuitry of claim 1 wherein the floating point number is in a format that is capable of representing negative numbers.

6. The floating point datapath circuitry of claim 1 further comprising a plurality of look-up table (LUT) circuitries for receiving the at least two bits of an unrounded mantissa of the floating point number.

7. The floating point datapath circuitry of claim 1 wherein the rounded absolute value of the mantissa is part of a mantissa of a signed magnitude format of a floating point number.

8. A method of computing a rounded absolute value of an unrounded mantissa of a floating point number, said method comprising:
receiving at least two bits of the unrounded mantissa of the floating point number; and
computing the rounded absolute value of a mantissa of the floating point number based on the at least two bits of the unrounded mantissa of the floating point number solely using a single adder.

9. The method of claim 8 wherein the at least two bits includes a sign bit.

10. The method of claim 8 wherein the at least two bits includes a sticky bit.

11. The method of claim 8 wherein the at least two bits includes a round bit.

12. The method of claim 8 wherein floating point number is in a format that is capable of representing negative numbers.

13. The method of claim 8 further comprising determining intermediate bits, using a plurality of look-up table circuitry, and based on the at least two bits, wherein the intermediate bits are used to compute the rounded absolute value of the mantissa of the floating point number.

14. The method of claim 8 wherein the rounded absolute value of the mantissa is part of a mantissa of a signed magnitude format of a floating point number.

15. Floating point datapath circuitry, said floating point datapath circuitry comprising:
solely a single adder stage for computing a rounded absolute value of a mantissa of a floating point number based on at least a sign bit of an unrounded mantissa of the floating point number.

16. The floating point datapath circuitry of claim 15 wherein the at least the sign bit includes the sign bit and a round bit.

17. The floating point datapath circuitry of claim 15 wherein the floating point number is in a format that is capable of representing negative numbers.

18. The floating point datapath circuitry of claim 15 further comprising a plurality of look-up table (LUT) circuitries for receiving the at least sign bit of an unrounded mantissa of the floating point number.

19. The floating point datapath circuitry of claim 15 wherein the rounded absolute value of the mantissa is part of a mantissa of a signed magnitude format of a floating point number.

20. The floating point datapath circuitry of claim 15 wherein a first adder in the single adder stage outputs its result to a second adder in the single adder stage to compute a least significant bit of the rounded absolute value of the mantissa based on the at least the sign bit.

Assignees

• Altera Corp

Inventors

• Langhammer Martin
• Pasca Bogdan

Classifications

• G06F7/49915 Primary

  Mantissa overflow or underflow in handling floating-point numbers · CPC title

• G06F7/48

  using non-contact-making devices, e.g. tube, solid state device; using unspecified devices · CPC title

• G06F7/49957

  Implementation of IEEE-754 Standard · CPC title

• G06F7/483 Primary

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title