Rounding floating point numbers

Patent metadata

Field	Value
Publication number	US-9489174-B2
Application number	US-201414498183-A
Country	US
Kind code	B2
Filing date	Sep 26, 2014
Priority date	Sep 26, 2014
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

Embodiments disclosed pertain to apparatuses, systems, and methods for floating point operations. Disclosed embodiments pertain to a circuit that is capable of processing both a normal and denormal inputs and outputting normal and denormal results, and where a rounding module is used advantageously to reduce operational latency of the circuit.

First claim

What is claimed is:

1. A floating point arithmetic unit comprising:
a rounding module configured to receive an unrounded result, the rounding module further comprising:
a multiplexer configured to select one of:
a first bitstring selected from a first plurality of bitstrings, wherein each bitstring in the first plurality of bitstrings comprises a corresponding bit sequence of the unrounded result, or
a second bitstring selected from a second plurality of bitstrings, wherein each bitstring in the second plurality of bitstrings comprises a corresponding bit sequence of an incremented result obtained by incrementing the unrounded result, and

wherein the selection of the first or second bitstring is based on bits in the unrounded result and is not dependent upon the incremented unrounded result.

2. The floating point arithmetic unit of claim 1 , wherein:
the output of the multiplexer represents a rounded floating point result.

3. The floating point arithmetic unit of claim 2 , wherein:
the rounded floating point result is a denormal floating point number.

4. The floating point arithmetic unit of claim 1 , wherein:
the floating point arithmetic unit is capable of performing at least one of a plurality of floating point operations comprising:
addition, or
subtraction, or
multiplication, or
division, or
fused multiplication-addition, or
square root determination, or
reciprocal determination, or
reciprocal square root determination, or
a transcendental function determination.

5. The floating point arithmetic unit of claim 1 , wherein:
one of the first plurality of bitstrings is obtained by appending a 1 bit to the corresponding bit sequence of the unrounded result.

6. The floating point arithmetic unit of claim 1 , wherein:
one of the second plurality of bitstrings is obtained by appending a 0 bit to the corresponding bit sequence of the incremented unrounded result; and
another of the second plurality of bitstrings is obtained by:
appending the corresponding bit sequence of the incremented normalized unrounded result to a 1 bit to obtain a partial bitstring, and
appending a 0 bit to the partial bitstring.

7. The floating point arithmetic unit of claim 1 , wherein:
the unrounded result is a denormal floating point number.

8. A processor comprising a floating point unit (FPU) configured to produce a rounded result, the FPU comprising:
a rounding module configured to receive an intermediate unrounded result of an operation performed by the FPU, the rounding module further comprising:
a multiplexer configured to select one of:
a first bitstring selected from a first plurality of bitstrings, wherein each bitstring in the first plurality of bitstrings comprises a corresponding bit sequence of the unrounded result, or
a second bitstring selected from a second plurality of bitstrings, wherein each bitstring in the second plurality of bitstrings comprises a corresponding bit sequence of an incremented result obtained by incrementing the unrounded result,

wherein the selection of the first or second bitstring is based on bits in the unrounded result and is not dependent upon the incremented unrounded result.

9. The processor of claim 8 , wherein:
the output of the multiplexer represents a rounded floating point result.

10. The processor of claim 9 , wherein:
the rounded floating point result is a denormal floating point number.

11. The processor of claim 8 , wherein the operation performed by the FPU comprises at least one of:
addition, or
subtraction, or
multiplication, or
division, or
fused multiplication-addition, or
square root determination, or
reciprocal determination, or
reciprocal square root determination, or
a transcendental function determination.

12. The processor of claim 8 , wherein:
one of the first plurality of bitstrings is obtained by appending a 1 bit to the corresponding bit sequence of the unrounded result.

13. The processor of claim 8 , wherein:
one of the second plurality of bitstrings is obtained by appending a 0 bit to the corresponding bit sequence of the incremented unrounded result; and
another of the second plurality of bitstrings is obtained by:
appending the corresponding bit sequence of the incremented normalized unrounded result to a 1 bit to obtain a partial bitstring, and
appending a 0 bit to the partial bitstring.

14. The processor of claim 8 , wherein:
the unrounded result is a denormal floating point number.

15. A non-transitory computer-readable medium comprising executable instructions to describe a floating point unit (FPU) capable of being configured to produce a rounded result, the FPU comprising:
a rounding module configured to receive an intermediate unrounded result of an operation performed by the FPU, the rounding module further comprising:
a multiplexer configured to select one of:
a first bitstring selected from a first plurality of bitstrings, wherein each bitstring in the first plurality of bitstrings comprises a corresponding bit sequence of the unrounded result, or
a second bitstring selected from a second plurality of bitstrings, wherein each bitstring in the second plurality of bitstrings comprises a corresponding bit sequence of an incremented result obtained by incrementing the unrounded result,

wherein the selection of the first or second bitstring is based on bits in the unrounded result and is not dependent upon the incremented unrounded result.

16. The computer-readable medium of claim 15 , wherein:
the output of the multiplexer represents a rounded floating point result.

17. The computer-readable medium of claim 16 , wherein:
the rounded floating point result is a denormal floating point number.

18. The computer-readable medium of claim 15 , wherein:
the operation performed by the FPU comprises at least one of:
addition, or
subtraction, or
multiplication, or
division, or
fused multiplication-addition, or
square root determination, or
reciprocal determination, or
reciprocal square root determination, or
a transcendental function determination.

19. The computer-readable medium of claim 15 , wherein:
one of the first plurality of bitstrings is obtained by appending a 1 bit to the corresponding bit sequence of the unrounded result.

20. The computer-readable medium of claim 15 , wherein:
one of the second plurality of bitstrings is obtained by appending a 0 bit to the corresponding bit sequence of the incremented unrounded result; and
another of the second plurality of bitstrings is obtained by:
appending the corresponding bit sequence of the incremented normalized unrounded result to a 1 bit to obtain a partial bitstring, and
appending a 0 bit to the partial bitstring.

21. The computer-readable medium of claim 15 , wherein:
the unrounded result is a denormal floating point number.

Assignees

• Imagination Tech Ltd
• Imagination Tech Ltd

Inventors

• Rarick Leonard

Classifications

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G06F7/483 Primary

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title

• G06F7/49957

  Implementation of IEEE-754 Standard · CPC title