Direct tunnel barrier control gates in a two-dimensional electronic system

Patent metadata

Field	Value
Publication number	US-9842921-B2
Application number	US-201414205811-A
Country	US
Kind code	B2
Filing date	Mar 12, 2014
Priority date	Mar 14, 2013
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A quantum semiconductor device is provided. The quantum semiconductor device includes a quantum heterostructure, a dielectric layer, and an electrode. The quantum heterostructure includes a quantum well layer that includes a first 2DEG region, a second 2DEG region, and a third 2DEG region. A first tunnel barrier exists between the first 2DEG region and the second 2DEG region. A second tunnel barrier exists between the second 2DEG region and the third 2DEG region. A third tunnel barrier exists either between the first 2DEG region and the third 2DEG region. The dielectric layer is formed on the quantum heterostructure. The electrode is formed on the dielectric layer directly above the first tunnel barrier.

First claim

What is claimed is:

1. A quantum semiconductor device comprising:
a quantum heterostructure comprising a quantum well layer, the quantum heterostructure configured to form a two-dimensional electron gas (2DEG) within the quantum well layer upon application of an electric field;
a dielectric layer composed of a dielectric material formed directly on the quantum heterostructure; and
a plurality of electrodes separated from each other and in direct contact with the dielectric layer, the plurality of electrodes comprising a first subset of electrodes and a second subset of electrodes,
wherein the first subset of electrodes is configured to delineate lateral boundaries of regions within the quantum well layer, the regions within the quantum well layer comprising a first quantum dot region having lateral dimensions sufficient to confine an electron of the 2DEG laterally in two dimensions to support formation of a first quantum dot within the quantum well layer; a second quantum dot region adjacent to the first quantum dot region and having lateral dimensions sufficient to confine another electron laterally in two dimensions to support formation of a second quantum dot within the quantum well layer; and a first quantum reservoir region adjacent to the first quantum dot region and having lateral dimensions larger than the lateral dimensions of each of the first and second quantum dot regions and sufficient to act as a source of a plurality of electrons of the 2DEG,
wherein the second subset of electrodes is configured to control electron accumulation and depletion within the regions within the quantum well layer,
wherein a first electrode belonging to the second subset of electrodes is positioned directly above the first quantum dot region,
a second electrode belonging to the second subset of electrodes is positioned directly above the second quantum dot region,
a third electrode belonging to the first subset of electrodes is positioned between the first and second electrodes and directly above a first tunnel barrier through which the electron tunnels from the first quantum dot region directly to the second quantum dot region along a first electron pathway within the quantum well layer,
and a fourth electrode belonging to the first subset of electrodes is positioned adjacent to the first electrode and directly above a second tunnel barrier through which the electron tunnels from the first quantum dot region directly to the first quantum reservoir region along a second electron pathway within the quantum well layer,
and further wherein the first, second, third and fourth electrodes are positioned such that the first electron pathway is coplanar but not collinear with the second electron pathway.

2. The quantum semiconductor device of claim 1 , wherein the dielectric material is an oxide material.

3. The quantum semiconductor device of claim 2 , wherein the oxide material is selected from the group consisting of Al 2 O 3 and HfO 2 .

4. The quantum semiconductor device of claim 1 , wherein the quantum well layer is formed of Si.

5. The quantum semiconductor device of claim 4 , the quantum heterostructure further comprising a first tunnel barrier layer formed on the quantum well layer and a cap layer formed on the first tunnel barrier layer, wherein the dielectric layer is formed on the cap layer.

6. The quantum semiconductor device of claim 5 , wherein the cap layer is formed of Si.

7. The quantum semiconductor device of claim 6 , the quantum heterostructure further comprising a second tunnel barrier layer, wherein the first tunnel barrier layer and the second tunnel barrier layer are formed of SiGe.

8. The quantum semiconductor device of claim 4 , the quantum heterostructure further comprising a first tunnel barrier layer formed on the quantum well layer, wherein the first tunnel barrier layer is formed of SiO 2 and the dielectric layer is formed on the first tunnel barrier layer.

9. The quantum semiconductor device of claim 1 , wherein the quantum well layer is formed of GaAs.

10. The quantum semiconductor device of claim 9 , the quantum heterostructure further comprising a first tunnel barrier layer formed on the quantum well layer and a cap layer formed on the first tunnel barrier layer, wherein the dielectric layer is formed on the cap layer.

11. The quantum semiconductor device of claim 10 , wherein the cap layer is formed of GaAs.

12. The quantum semiconductor device of claim 11 , wherein the first tunnel barrier layer is formed of Al x Ga 1-x As.

13. The quantum semiconductor device of claim 1 , the quantum heterostructure further comprising a first tunnel barrier layer, wherein the quantum well layer is formed on the first tunnel barrier layer, and the dielectric layer is formed on the quantum well layer.

14. The quantum semiconductor device of claim 13 , wherein the quantum well layer is formed of graphene.

15. The quantum semiconductor device of claim 13 , wherein the first tunnel barrier layer is formed of SiO 2 .

16. The quantum semiconductor device of claim 1 , wherein the first and second electrodes are on the surface of the dielectric layer, thereby forming an upper electrode layer, and the third and fourth electrodes are within the dielectric layer, thereby forming a lower electrode layer.

17. The quantum semiconductor device of claim 1 , wherein a fifth electrode belonging to the second subset of electrodes is positioned directly above the first quantum reservoir region.

18. The quantum semiconductor device of claim 1 , wherein the first subset of electrodes is further configured to delineate lateral boundaries of a second quantum reservoir region adjacent to the second quantum dot region and having lateral dimensions larger than the lateral dimensions of each of the first and second quantum dot regions and sufficient to act as another source of a plurality of electrons of the 2DEG,
wherein a fifth electrode belonging to the first subset of electrodes is positioned adjacent to the second electrode and directly above a third tunnel barrier through which the another electron tunnels from the second quantum dot region directly to the second quantum reservoir region along a third electron pathway within the quantum well layer,
and further wherein the fifth electrode is positioned such that the third electron pathway is coplanar but not collinear with the first electron pathway.

19. The quantum semiconductor device of claim 18 , wherein the first subset of electrodes is further configured to delineate lateral boundaries of an additional region adjacent to the first quantum dot region into which the electron tunnels directly from the first quantum dot region via a fourth tunnel barrier,
wherein the additional region is a third quantum reservoir region or a third quantum dot region,
and further wherein a sixth electrode belonging to the second subset of electrodes is positioned to a side of the first electrode and directly above the additional region.

20. The quantum semiconductor device of claim 19 , wherein the first subset of electrodes is further configured to delineate lateral boundaries of a fourth quantum reservoir region adjacent to the second quantum dot region into which the another electron tunnels directly from the second quantum dot region via a fifth tunnel barrier,
and further wherein a seventh electrode belonging to the second subset of electrodes is positioned to a side of the second electrode and directly above the fourth quantum reservoir region.

21. The quantum semicon

Assignees

• Wisconsin Alumni Res Found

Inventors

• Eriksson Mark A
• Gamble John King
• Ward Daniel R
• Coppersmith Susan Nan
• Friesen Mark G

Classifications

• H01L29/778

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic

• H01L29/127

  Electricity · mapped topic

• H01L29/7782 Primary

  Electricity · mapped topic

• H01L29/413

  Electricity · mapped topic