Germanium-based quantum well devices

Patent metadata

Field	Value
Publication number	US-9478635-B2
Application number	US-201514924643-A
Country	US
Kind code	B2
Filing date	Oct 27, 2015
Priority date	Dec 30, 2009
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

First claim

We claim:

1. A method of fabricating a microelectronic device, comprising:
forming a lower barrier region comprising a large band gap material;
forming a quantum well channel region comprising germanium on the lower barrier region;
forming an upper barrier region comprising a large band gap material on the quantum well region;
forming a spacer region on the quantum well channel region;
forming an etch stop region on the spacer region, the etch stop region comprising silicon and being substantially free from germanium;
forming a gate dielectric on the etch stop region;
forming a gate electrode on the gate dielectric;
forming a doped region on the lower barrier region, the doped region comprising silicon germanium doped with boron; and
forming a lower spacer region comprising silicon germanium on the doped region and under the quantum well channel region.

2. The method of claim 1 , wherein forming the spacer region on the quantum well channel region comprises forming a silicon germanium spacer region on the quantum well channel region.

3. The method of claim 1 , wherein forming the gate dielectric on the etch stop region comprises forming the gate dielectric directly on the etch stop region.

4. The method of claim 1 , wherein forming the etch stop region on the spacer region comprises forming a first portion comprising silicon and forming a second portion on the first portion.

5. The method of claim 4 , wherein forming the second portion comprises forming a silicon dioxide second portion.

6. The method of claim 5 , wherein forming the gate dielectric on the etch stop region comprises forming the gate dielectric directly on the second portion of the etch stop region.

7. The method of claim 1 , wherein forming the etch stop region on the spacer region comprises forming the etch stop region on the etch stop region, wherein the etch stop region has a thickness of less than twenty angstroms.

8. The method of claim 1 , wherein forming the lower barrier region comprises forming a silicon germanium lower barrier region.

9. The method of claim 1 , wherein forming the lower barrier region comprises forming the lower barrier region from a group III-V material.

10. The method of claim 9 , wherein forming the lower barrier region comprises forming a GaAs lower barrier region.

11. The method of claim 1 , wherein forming the upper barrier region comprises forming a silicon germanium upper barrier region.

12. The method of claim 1 , wherein forming the upper barrier region comprises forming the lower barrier region from a group III-V material.

13. The method of claim 1 , wherein forming the lower barrier region, forming the quantum well channel region, forming the upper barrier region, forming the spacer region, forming the etch stop region, forming the gate dielectric, and forming the gate electrode are all part of forming a p-type transistor, and further comprises forming an n-type transistor comprising:
forming a lower barrier region comprising a group III-V material;
forming a quantum well channel region comprising a group III-V material on the lower barrier region;
forming an upper barrier region comprising a group III-V material on the quantum well region;
forming a gate dielectric on the quantum well channel region and not in contact with the quantum well channel region; and
forming a gate electrode on the gate dielectric.

14. The method of claim 1 , wherein forming the lower barrier region, forming the quantum well channel region, forming the upper barrier region, forming the spacer region, forming the etch stop region, forming the gate dielectric, and forming the gate electrode are all part of forming a p-type transistor, and further comprises forming an n-type transistor comprising:
forming a source region in a substrate;
forming a drain region in the substrate;
forming a channel region in the substrate and between the source and drain regions;
forming a gate dielectric on the channel region, wherein the channel region has side walls;
forming a gate electrode on the gate dielectric and having side walls; and
forming spacers adjacent the side walls of the gate dielectric and adjacent the side walls of the gate electrode.

Assignees

• Intel Corp

Inventors

• Pillarisetty Ravi
• Jin Been-Yih
• Chu-Kung Benjamin
• Metz Matthew V
• Kavalieros Jack T
• Radosavljevic Marko
• Kotlyar Roza
• Rachmady Willy
• Mukherjee Niloy
• Dewey Gilbert
• Chau Robert S

Classifications

• H10P14/3421

  Arsenides · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D30/015

  of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT · CPC title