Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9287409-B2
Application number	US-201414540365-A
Country	US
Kind code	B2
Filing date	Nov 13, 2014
Priority date	Jun 17, 2011
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

One object of the present invention is to provide a structure of a transistor including an oxide semiconductor in a channel formation region in which the threshold voltage of electric characteristics of the transistor can be positive, which is a so-called normally-off switching element, and a manufacturing method thereof. A second oxide semiconductor layer which has greater electron affinity and a smaller energy gap than a first oxide semiconductor layer is formed over the first oxide semiconductor layer. Further, a third oxide semiconductor layer is formed to cover side surfaces and a top surface of the second oxide semiconductor layer, that is, the third oxide semiconductor layer covers the second oxide semiconductor layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first oxide semiconductor layer;
a second oxide semiconductor layer over the first oxide semiconductor layer;
a third oxide semiconductor layer provided over the second oxide semiconductor layer to cover side surfaces of the second oxide semiconductor layer;
a source electrode layer and a drain electrode layer over the third oxide semiconductor layer;
a gate insulating film over the source electrode layer and the drain electrode layer; and
a gate electrode layer over the gate insulating film to overlap with the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer,
wherein the second oxide semiconductor layer has a smaller energy gap than the first oxide semiconductor layer and the third oxide semiconductor layer,
wherein the third oxide semiconductor layer comprises crystals of which c-axes are aligned substantially in one direction.

2. The semiconductor device according to claim 1 ,
wherein the third oxide semiconductor layer is in contact with part of a top surface of the first oxide semiconductor layer.

3. The semiconductor device according to claim 1 ,
wherein the first oxide semiconductor layer is formed over and in contact with an oxide insulating film, and
wherein in the oxide insulating film, a thickness of a region in contact with the third oxide semiconductor layer is smaller than a thickness of a region in contact with the first oxide semiconductor layer.

4. The semiconductor device according to claim 1 ,
wherein the second oxide semiconductor layer has greater electron affinity than the first oxide semiconductor layer and the third oxide semiconductor layer.

5. The semiconductor device according to claim 1 ,
wherein the third oxide semiconductor layer covers entirely side surfaces of the second oxide semiconductor layer.

6. The semiconductor device according to claim 1 ,
wherein the second oxide semiconductor layer comprises In—Sn—Zn—based oxide.

7. The semiconductor device according to claim 1 ,
wherein the c-axes are aligned substantially perpendicular to a surface of the second oxide semiconductor layer.

8. The semiconductor device according to claim 1 ,
wherein the second oxide semiconductor layer has a hydrogen concentration lower than or equal to 5×10 19 /cm 3 .

9. The semiconductor device according to claim 1 ,
wherein the third oxide semiconductor layer comprises In, Ga, Zn and O.

10. A semiconductor device comprising:
a first oxide semiconductor layer;
a second oxide semiconductor layer over the first oxide semiconductor layer;
a third oxide semiconductor layer provided over the second oxide semiconductor layer to cover side surfaces of the second oxide semiconductor layer;
a gate electrode layer overlapped with the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer; and
a gate insulating film between the gate electrode layer and a stack of the first, second and third oxide semiconductor layers,
wherein the second oxide semiconductor layer has a smaller energy gap than the first oxide semiconductor layer and the third oxide semiconductor layer, and
wherein the third oxide semiconductor layer comprises crystals of which c-axes are aligned substantially in one direction.

11. The semiconductor device according to claim 10 ,
wherein the third oxide semiconductor layer is in contact with part of a top surface of the first oxide semiconductor layer.

12. The semiconductor device according to claim 10 ,
wherein the first oxide semiconductor layer is formed over and in contact with an oxide insulating film, and
wherein in the oxide insulating film, a thickness of a region in contact with the third oxide semiconductor layer is smaller than a thickness of a region in contact with the first oxide semiconductor layer.

13. The semiconductor device according to claim 10 ,
wherein the second oxide semiconductor layer has greater electron affinity than the first oxide semiconductor layer and the third oxide semiconductor layer.

14. The semiconductor device according to claim 10 ,
wherein the third oxide semiconductor layer covers entirely side surfaces of the second oxide semiconductor layer.

15. The semiconductor device according to claim 10 ,
wherein the second oxide semiconductor layer comprises In—Sn—Zn—based oxide.

16. The semiconductor device according to claim 10 ,
wherein the c-axes are aligned substantially perpendicular to a surface of the second oxide semiconductor layer.

17. The semiconductor device according to claim 10 ,
wherein the second oxide semiconductor layer has a hydrogen concentration lower than or equal to 5×10 19 /cm 3 .

18. The semiconductor device according to claim 10 ,
wherein the third oxide semiconductor layer comprises In, Ga, Zn and O.

19. A semiconductor device comprising:
a first oxide semiconductor layer;
a second oxide semiconductor layer over the first oxide semiconductor layer;
a third oxide semiconductor layer provided over the second oxide semiconductor layer to cover side surfaces of the second oxide semiconductor layer;
a source electrode layer and a drain electrode layer over the third oxide semiconductor layer, each of the source electrode layer and the drain electrode layer comprising a first conductive layer comprising tantalum nitride and a second conductive layer comprising copper, wherein the first conductive layers are in direct contact with the third oxide semiconductor layer;
a gate insulating film over the source electrode layer and the drain electrode layer; and
a gate electrode layer over the gate insulating film to overlap with the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer,
wherein the second oxide semiconductor layer has a smaller energy gap than the first oxide semiconductor layer and the third oxide semiconductor layer.

20. The semiconductor device according to claim 19 ,
wherein the third oxide semiconductor layer is in contact with part of a top surface of the first oxide semiconductor layer.

21. The semiconductor device according to claim 19 ,
wherein the first oxide semiconductor layer is formed over and in contact with an oxide insulating film, and
wherein in the oxide insulating film, a thickness of a region in contact with the third oxide semiconductor layer is smaller than a thickness of a region in contact with the first oxide semiconductor layer.

22. The semiconductor device according to claim 19 ,
wherein the second oxide semiconductor layer has greater electron affinity than the first oxide semiconductor layer and the third oxide semiconductor layer.

23. The semiconductor device according to claim 19 ,
wherein the third oxide semiconductor layer covers entirely side surfaces of the second oxide semiconductor layer.

24. The semiconductor device according to claim 19 ,
wherein the second oxide semiconductor layer comprises In—Sn—Zn—based oxide.

25. The semiconductor device according to claim 19 ,
wherein the second oxide semiconductor layer has a hydrogen concentration lower than or equal to 5×10 19 /cm 3 .

26. The semiconductor device according to claim 19 ,
wherein the third oxide semiconductor layer comprises In, Ga, Zn and O.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Honda Tatsuya

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6758

  characterised by the insulating substrates · CPC title

• H10D30/473

  having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT · CPC title

• H10D30/031

  of thin-film transistors [TFT] · CPC title

• H10D62/82

  Heterojunctions · CPC title