Semiconductor wafer including a monocrystalline semiconductor layer spaced apart from a poly template layer

Patent metadata

Field	Value
Publication number	US-9842899-B2
Application number	US-201514966649-A
Country	US
Kind code	B2
Filing date	Dec 11, 2015
Priority date	Mar 15, 2013
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A semiconductor wafer can include a substrate, a poly template layer, and a semiconductor layer. The substrate has a central region and an edge region, the poly template layer is disposed along a peripheral edge of the substrate, and a semiconductor layer over the central region, wherein the semiconductor layer is monocrystalline. In an embodiment, the poly template layer and the monocrystalline layer are laterally spaced apart from each other by an intermediate region. In another embodiment, the semiconductor layer can include aluminum. A process of forming the substrate can include forming a patterned poly template layer within the edge region and forming a semiconductor layer over the primary surface. Another process of forming the substrate can include forming a semiconductor layer over the primary surface and removing a portion of the semiconductor layer so that the semiconductor layer is spaced apart from an edge of the substrate.

First claim

What is claimed is:

1. A semiconductor wafer comprising:
a substrate having a primary surface that has a central region, an edge region, and an intermediate region disposed between the central region and the edge region;
wherein:
the central region comprises at least two semiconductor layers and a gate dielectric layer, wherein the at least two semiconductor layers of the central region are monocrystalline,
the edge region lies along a side surface of the substrate and comprises at least two semiconductor layers, a gate dielectric layer, a pad layer, and a poly template layer, wherein the at least two semiconductor layers of the edge region are polycrystalline, and
the intermediate region is disposed between the central region and the edge region and does not include any portion of each of the at least two semiconductor layers of the central or edge region, the gate dielectric layer of the central or edge region, the pad layer of the edge region, and the poly template layer of the edge region.

2. The semiconductor wafer of claim 1 , wherein the at least two semiconductor layers of the central and edge regions comprise a first semiconductor layer and a second semiconductor layer, the first semiconductor layer comprising a GaN layer.

3. The semiconductor wafer of claim 2 , wherein the second semiconductor layer of the central and edge regions further comprises a first AlGaN layer.

4. The semiconductor wafer of claim 3 , wherein the at least two semiconductor layers of the central and edge regions further comprise a third semiconductor layer that is monocrystalline in the central region and polycrystalline in the edge region, the third semiconductor layer comprising a second AlGaN layer, wherein the GaN layer is disposed between the first and second AlGaN layers.

5. The semiconductor wafer of claim 3 , further comprising an aluminum nitride layer disposed between the substrate and the first AlGaN layer, wherein the intermediate region does not contain the aluminum nitride layer.

6. The semiconductor wafer of claim 1 , wherein the monocrystalline portion of the at least two semiconductor layers has a sloped edge adjacent to central region.

7. The semiconductor wafer of claim 6 , wherein the sloped edge lies along a plane that intersects the primary surface at an angle no greater than 30°.

8. The semiconductor wafer of claim 1 , wherein the gate dielectric layer has a sloped edge.

9. The semiconductor wafer of claim 1 , wherein the intermediate region, the edge region, or each of the intermediate and edge regions is no greater than 9 mm wide.

10. The semiconductor wafer of claim 1 , wherein the poly template layer comprises an oxide film.

11. The semiconductor wafer of claim 1 , wherein the pad layer includes a silicon dioxide film, and the poly template layer includes a silicon nitride film disposed over the pad layer.

12. The semiconductor wafer of claim 11 , further comprising an AlN layer disposed between the substrate and the at least two semiconductor layers of the central and edge regions, wherein the intermediate region does not contain the AlN layer.

13. The semiconductor wafer of claim 12 , wherein the at least two semiconductor layers include a buffer layer over the AlN layer, a GaN layer over the buffer layer, and a barrier layer over the GaN layer.

14. The semiconductor wafer of claim 13 , wherein the substrate is a monocrystalline silicon wafer.

15. The semiconductor wafer of claim 13 , wherein the at least two semiconductor layers of the central region have a sloped edge.

16. The semiconductor wafer of claim 15 , wherein the sloped edge lies along a plane that intersects the primary surface at an angle no greater than 30°.

17. The semiconductor wafer of claim 16 , wherein the gate dielectric layer overlies the barrier layer.

18. The semiconductor wafer of claim 17 , wherein the gate dielectric layer includes one or more nitride films.

19. The semiconductor wafer of claim 17 , wherein the each of the outer edges of the at least two semiconductor layers and the gate dielectric layer within the central region has a sloped edge that lies along a plane that intersects the primary surface at an angle no greater than 30°.

20. The semiconductor wafer of claim 19 , wherein the substrate is a monocrystalline silicon wafer.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Ziad Hocine Bouzid
• Moens Peter
• De Backer Eddy

Classifications

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10P14/2926

  Crystal orientations · CPC title

• H10P90/128

  by edge treatment, e.g. chamfering · CPC title

• H10P70/54

  Cleaning of wafer edges · CPC title

• H10P14/3458

  Monocrystalline · CPC title